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IRSIM To-Do List

1. (FIXED) Fix the print menu options in the Tcl version (Tcl script issue)
2. (FIXED) Fix the legend printing (PostScript issue)
3. (FIXED) Fix stepsize vs. modern technologies
4. Propagating undefined ("X") values

1. (FIXED) Fix the print menu options in the Tcl version (Tcl script issue)

2. (FIXED) Fix the legend printing (PostScript issue)

3. (FIXED) Fix stepsize vs. modern technologies

As pointed out by Wei Zhang, the 10ps stepsize runs up against the capabilities of modern processes. In base/net.h, sometime in the past, it looks like someone changed the default internal stepsize from 100ps to 10ps simply by redefining the stepsize-to-real-time conversion factors. This could be changed again to 1ps, but it seems better to add a command or command option (e.g., extend the "stepsize" command with an option) that would allow any conversion factor to be set (and preferably to be set at any time, scaling internal values as necessary).
This has been fixed; the current version has an internal stepsize of 1ps and declares the typecast of the time variable to be "unsigned long long", or 64 bits, so you can simulate to 9223372 seconds total simulation time, or 106 virtual days. There is no penalty to having a stepsize of 1ps, so there does not appear to be any particular reason to allow an arbitrary stepsize.

4. Propagating undefined ("X") values

IRSIM is notorious for the usual way in which switch simulators fall over onto their face, which is handling positive-feedback loops such as SRAMs and many standard flip-flop designs. I added the "settle value" command, which goes a long way toward preventing this problem, but I've still seen it happen anyway. Please send along examples to the developer (tim at opencircuitdesign dot com) if you find them.

More recently (summer 2007) I found a way to get around most of the other problems caused by larger, more subtle feedback loops. This is the new command "relax type". It may be issued at any point in the simulation. What it does is to find all undefined nodes and force each one to a specific high or low logic level. It does this in the same way as would a "h" or "l" command, but the node is never specified as a driven input, so it is not forced to remain at this value. This suffices to get through most initialization problems. The argument "type" may be one of "l", "h", or "r", where "l" and "h" attempt to force each undefined node low or high, respectively, while "r" randomly selects a low or high value for each undefined node encountered. If you're unsure of the validity of results using the "relax" command, try running the simulation several times using "relax r". If you keep getting the same result, then your circuit is probably okay.


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Last edited September 15, 2007 3:07 am by R. Timothy Edwards (diff)
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