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Magic To-Do List

1. Items needing attention
1.1. Extresist
1.2. Standard Extraction
1.3. Behavior of "see" command
1.4. CIF-DRC rules
1.5. Add an extension to the DRC statement "spacing" to cover spacing exceptions
1.6. Create an updated (and online) version of the Maintainer's Manual 3
1.7. Maze Router (work in progress, August 2006)
1.8. Plow
1.9. Plotting
2. Completed items
2.1. (Done) Plotting
2.2. (Done) Add an extension to the DRC statement "overhang" for option "absence_ok"
2.3. (Done) Add an extension to allow a much-simplified description of overlap and area capacitances
2.4. (Done) Error: DRC statement "surround" does not allow ...
2.5. (Done) Error: DRC statement "maxwidth" does not ...
2.6. (Done) Extend the "spacing" rule to allow "touching_ok"
2.7. (Done) Layer and cell locking
2.8. (Done) Asymmetric Device Extraction
2.9. Subcircuit Device Extraction Extensions
2.10. (Done) Rendered Font Labels

1. Items needing attention

1.1. Extresist

The "extresist" code only recognizes original "fet" types, not the new "device" types in the extract file. I have several submitted examples of "extresist" fouling up a netlist, and these need to be investigated and fixed. The larger part of the code has not been updated to take advantage of new features of magic 7.4 and 7.5.

1.2. Standard Extraction

There should be some method for identifying devices inside marker layers, as well as the standard device layer types (especially useful for inductors, diodes, and lateral bipolar devices).

1.3. Behavior of "see" command

The behavior of the "see" command was changed to allow contact residues to be seen (e.g., "see no *; see m1" results in the appearance of metal1 where vias, poly contacts, diffusion contacts, etc., were. However, when the contact layers are not visible, they also cannot be selected. This behavior is a bit disconcerting. It would be preferable in this case to always treat the contact as containing the visible material, such that (in this example) selecting the contact would copy metal1 into the selection.

1.4. CIF-DRC rules

These rules are largely equivalent to the way Calibre does DRC, processing layers by boolean operators. The paint left over at the end of processing a rule's operators make up the error. The CIF-DRC rules need several updates:

1.5. Add an extension to the DRC statement "spacing" to cover spacing exceptions

Add an extension to the DRC statement "spacing" to cover spacing exceptions. This happens fairly regularly, for example, when diffusion-to-diffusion spacing is 3 but the minimum transistor length is 2. The standard "spacing" rule doesn't work in such a case, and you need two ugly edge4way rules, one to handle the original spacing rule and another to handle the exception. I propose a rule variant similar to the "bloat" rule in the cifoutput section: "spacing typesA typesB * dist1 typesC dist2 typesD dist3 ...". For example, "spacing *ndiff *ndiff * 3 nfet 2 ..." would handle the case described above.

1.6. Create an updated (and online) version of the Maintainer's Manual 3

Create an updated (and online) version of the Maintainer's Manual 3, explaining the ins and outs of the colormap and display files, stipple patterns, transparency effects, etc. A great deal of this has been changed and is not documented anywhere.

1.7. Maze Router (work in progress, August 2006)

Maze Router (work in progress, August 2006). I have already identified and corrected several awful bugs in this code. I'm still waffling about whether or not to rewrite the thing from scratch. I have already implemented connectivity checks around start and destination points. Major errors were 1) painting blockage information into all planes simultaneously, so that, for example, a metal1 obstruction would prevent the maze router from simply routing over it in metal2, and 2) recording start and destination tiles in the cell definition where they occur, thus failing to create blockage information around the same pin in other instances of the cell that might be present in the layout. Currently, I'm looking at a few more instances of sub-optimal routing in simple situations, but the behavior is already much better than it was previously. I would like to get rid of the "DBPaintPlaneVert" routine, since you don't need a separate routine to implement a "maximum vertical stripes" rule for the corner stitched database, since it can be much more simply implemented just by swapping X and Y coordinates. These fixes to the router code are in conjunction with development of a complete Verilog-to-layout flow (for which the maze router is the only part that doesn't work).

1.8. Plow

Part of the Maze Router work included picking up DRC rules from the DRC database. When I did this, I ripped out the DRC rule values local to the maze router database; this action forced me to do the same to the DRC rule values local to the plow database, too. Consequently, the "plow" command is broken, and needs to be fixed.

1.9. Plotting

The plotting command is a bit haphazardly implemented. Various aspects of the command need to be consolidated so that it is effectively divided into four parts: scaling (pixel, inch, cm, or magnification), method (simple raster, color raster, color-blend, and vector), format (PostScript, PNM, HPRTL, HPGL2), and output (file or printer spooler). Each of these four parts should be independent from one another. The LLNL "plot pixel" should be updated and merged into the HPRTL/HPGL2 code to implement full-color rasters in addition to the simple CMY-plane rasters. The "plot pnm" code should have more features, such as border and cross options. All methods should allow a "contact cut" style which plots the actual contact cuts. This might mean, in effect, a choice of magic database or CIF/GDS database for output.

2. Completed items

2.1. (Done) Plotting

Implementation of HPRTL and HPGL2 on top of the existing color Versatec driver. Also added a way to filter PNM plots through the HPRTL and HPGL2 filters.

2.2. (Done) Add an extension to the DRC statement "overhang" for option "absence_ok"

Add an extension to the DRC statement "overhang" for option "absence_ok". Probably this would make more intuitive sense if the statement was changed from "overhang" to "extend", with option "absence_illegal" being equivalent to the "overhang" statement (which would then be deprecated). "extend ... absence_ok" effectively implements edge4way A B <d> ~A B <d> "why" <plane>
Done, except that I opted for the new DRC statement "extend" to cover this case

2.3. (Done) Add an extension to allow a much-simplified description of overlap and area capacitances

Add an extension of the extraction section statements to allow a much-simplified description of overlap and area capacitances. Currently, a correct extraction section requires redundant declarations of symmetric situations, and other inefficiencies.
Done. The online Maintainer's Manual #2 has been updated with a description of these commands and their syntax. The extract parasitic capacitance has now been reduced to something that can be entered in a few minutes by copying out of the foundry electrical parameters document. I also added a command "units microns" to allow capacitance values to be entered in the more convenient units of aF/um and aF/um^2 instead of the awkward aF/lambda and aF/lambda^2.

2.4. (Done) Error: DRC statement "surround" does not allow ...

Error: DRC statement "surround" does not allow types on the inside edge to be in the list of "ok" types, although this is quite common (e.g., metal 2 surrounds via should allow another via to be in the surround region).
Fixed. "surround" may now include the inside type in the list of outside types, which is interpreted in the obvious way, and does not flag a warning about false edges.

2.5. (Done) Error: DRC statement "maxwidth" does not ...

Error: DRC statement "maxwidth" does not round down as it should when the rule is not an integer number of internal units.

2.6. (Done) Extend the "spacing" rule to allow "touching_ok"

In response to a request from Oliver Banzhaf: extend the "spacing" rule to allow "touching_ok" for types on different planes. The effect would be to compute the spacing from the edge to the type except when the type touches or overlaps the edge. This allows, for example, rules like "spacing nwell ndiff" while allowing ndiff to represent both ndiff and nsd (ndiff in nwell). However, it may be better to have a more comprehensive rule that allows one to specify an "edge" between any two types, regardless of whether or not they are on the same plane. Then the above spacing rule can be implemented as a type of "edge4way" rule. I just thought of a reasonably simple way to code this using the "trigger" rule that I devised to implement the widespacing rule: rule "B surround A" triggers rule "spacing A to C <= d" (actually it's the violation of a rule that acts as the trigger of the second rule, but this is easily implemented as an edge4way rule). (Also done)

2.7. (Done) Layer and cell locking

Implement a command to lock specific layers and cell instances (cell uses). This helps to prevent unintentional changes when making back-end modifications to an existing design.
Done, January 2008. Cell locking is accomplished by selecting a cell instance and typing the command "instance lock". Layer locking is accomplished by the command "tech layer lock". Revision 7.5.104 and the corresponding 7.4 version (January 5) correct inconsistencies in the handling of contacts by layer locking. Update January 7: Made more corrections; result now looks okay with respect to stacked contacts as well as everything else.

2.8. (Done) Asymmetric Device Extraction

Need to be able to specify a FET type with non-equivalent source and drain, as happens with high-voltage and ESD devices. This can be done now with the standard "device fet" line simply by specifying two separate type lists for source and drain. The rest is handled automatically.

2.9. Subcircuit Device Extraction Extensions

It is possible now (as of around May 2009) to specify parameter key:value pairs in the description of a subcircuit device extraction. These parameters will be passed to the subcircuit in a manner compatible with most versions of SPICE. A number of standard parameters for device properties that the magic extractor can determine are provided, such as device area, perimeter, length, width, capacitance, substrate node, and position.

2.10. (Done) Rendered Font Labels

Magic version 8.0 implements vector-drawn labels using rendered outline fonts that can be rotated, scaled, and justified arbitrarily. The implementation uses OpenGL and open-source outline fonts from the "freefont" project (you gotta love open source!). The X11 version is implemented somewhat less optimally, but is also complete. Version 8.0 comes with three scalable fonts: FreeMono (Courier), FreeSans (Helvetica), and FreeSerif (Times). An extended version of the "label" command generates labels with fonts, and a new command "setlabel" manipulates selected labels. A GUI window would be nice for making some of the messiness of the extended "label" and "setlabel" commands transparent to the end-users. As a minor implementation note: OpenGL should use display lists to the extent possible; since this is a speed optimization, not a necessity, it has not been implemented yet.

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Last edited July 10, 2009 11:30 pm by Tim Edwards (diff)
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