Calibre (my only other reference for LVS) works, as far as I can tell, by doing network matches first and then listing any property errors at the end. There's a tolerance specified for how well the property must match (e.g., 1-2 percent for capacitors and resistors, usually exact value necessary for FET length and width).
I added property checks in Netgen in December 2007. The way I implemented it, property checks are only made on unique element classes. So no property check is made until Netgen has determined a 1-to-1 match between a device in each of the two netlists being compared. A property mismatch will not prevent completion of the matching algorithm. If the circuits are a topological match but have property differences, netgen will report the property errors. Currently resistor and capacitor values, and transistor width and length, are compared properties, and match with a tolerance of 1 percent. I will add command-line commands to add new properties to compare and change the tolerances. However, property checking is strongly related to parallel/serial reduction, which I have not yet worked on in netgen.