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Netgen To-Do List

1. Items requiring attention
1.1. add property generation and tolerance setting
1.2. add hierarchical LVS subcircuit port mapping
1.3. add hierarchical LVS overall comparison summary
1.4. add side-by-side comparison result output format
1.5. add device parallel and serial merging
1.6. other netlist manipulations
2. Items completed
2.1. add property check
2.2. add hierarchical checks

1. Items requiring attention

1.1. add property generation and tolerance setting

There needs to be a "property" command that allows properties other than the default ones to be compared during LVS, and a command option that allows one to set the tolerance for a pass/fail result on a property match.

1.2. add hierarchical LVS subcircuit port mapping

The hierarchical LVS needs to check whether the port order is the same or not between equivalent subcircuits in the two top-level cells being compared. If not, one of them needs to have its pins re-mapped to match the other.

1.3. add hierarchical LVS overall comparison summary

The output file from hierarchical LVS needs to finish with a succinct list of the matching result for each pair of subcircuits checked.

1.4. add side-by-side comparison result output format

The side-by-side output is much easier to parse than the current line-by-line format.

1.5. add device parallel and serial merging

Should be able to do parallel merges of capacitors, parallel/serial merges of resistors, and parallel merges of transistors. Need a command "merge" to handle this (to be executed in the LVS script between "compare" and "run").

1.6. other netlist manipulations

Add option to remove dummy FETs (pFETs with gate tied to VDD or nFETs with gate tied to ground).

2. Items completed

2.1. add property check

Completed (but not thoroughly checked), December 2007. Netgen now reads standard properties like length and width of transistors, and resistor and capacitor values, and reports whether the properties match between the two lists being compared. The implementation allows checking of integer, string, and floating-point values, although currently only floating-point values are known to the SPICE read routine. Floating-point values are compared to within 1 percent. There is not yet any method to change this "slop" allowance, although the slop value is implemented in the code.

2.2. add hierarchical checks

Completed, except for the necessary addition of port order mapping between subcircuits (see above). The code version 1.4.6 implements the basic hierarchical check algorithm. The "lvs" script calls the hierarchical check. Netgen descends the hierarchy of both circuits to be compared, and finds all known matches between subcircuits, either by name, or by explicit declaration of equivalence in the setup file. All subcircuits that cannot be matched are flattened. Netgen then runs a full LVS on each of the known matching pairs of subcircuits. As of version 1.4.6 there is no overall summary of results, so subcircuit results are buried in the output log file, which is potentially misleading (also see above).


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Last edited January 8, 2008 2:06 am by R. Timothy Edwards (diff)
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