Netgen 1.5

Table of Contents

Revision information on Netgen 1.5
Revision information on Netgen 1.4
Revision information on Netgen 1.3
Revision information on Netgen 1.2
Revision information on Netgen 1.1

Revision information on Netgen 1.5:

Netgen revision history: Version 1.5

• posted: April 4, 2024 at 2:00am     version: 1.5     revision: 273
  Corrected an error that had previously been corrected in PropertyMatch() but not corrected symmetrically between circuit1 and circuit2; this left the possibility that "M=1" in one circuit vs. no "M" entry in the other would still pop up as a property error, depending on which circuit (layout or schematic) was listed first.
  Corrected another error in which, for device sorting, "M" was set to 1 before the loop over devices in "run", resulting in "M" taking the value of the previous property record if the following record did not have an "M" value, instead of setting it to 1.
  
• posted: March 5, 2024 at 2:00am     version: 1.5     revision: 272
  Corrected an issue that prevents "cells list " from reporting empty cells (this does not solve the problem at hand, but is a part of it).
  
• posted: February 20, 2024 at 2:00am     version: 1.5     revision: 271
  Removed the requirement for package "m4" that is in the configuration script. It is not needed and doesn't exist in many OS distributions.
  Also updated configure (in addition to configure.in) with the change to remove the "m4" dependency.
  
• posted: February 19, 2024 at 2:00am     version: 1.5     revision: 270
  Having been given an example by Kareem Farid where the order of verilog netlists makes a difference to the matching (or failure thereof), I applied the same in-circuit pin matching as previously applied to mixtures of SPICE and verilog netlists. This is clearly a more robust way to handle pin order differences between parent and child than was implemented previously.
  
• posted: February 10, 2024 at 2:00am     version: 1.5     revision: 269
  Corrected an issue that arose due to a change made earlier: A while back, shorted pins were moved into contiguous positions. When that method was discovered to cause matching issues, it was abandoned with a note that doing so might have unintended consequences because other code might depend on the shorted pins being contiguous. Such a case was just found, and corrected. However, it was also found that shorted pins were still not completely handled correctly in MatchPins(); a solution was found that adds such pins to the "permutes" list (which needs to be done if the shorted pins are to be correctly handled in any higher level of the hierarchy, if there is one), and the "permutes" list is then checked by MatchPins() to determine if pins match because they belong to the same group of shorted pins.
  
• posted: February 7, 2024 at 2:00am     version: 1.5     revision: 268
  Found an error with the property sorting in which float values were not compared for sorting in the same way they are compared for property matching. The "slop" value was treated as absolute, not a percentage, so for example a slop of 0.01 on a dimension of microns would cause all dimensions to be treated as round-off error, and no sorting would occur.
  Corrected another error in which some simple expressions are incorrectly evaluated; "(w+l)" for example treats "w+l" as a single string instead of three tokens. Corrected the code to watch for a failure of strtod() when parsing the expression at the "+" sign (also for "-").
  
• posted: February 4, 2024 at 2:00am     version: 1.5     revision: 267
  Added code to handle the problem in which a verilog netlist is read before its component cells, and the component cells are read in as SPICE netlists. Then the original verilog cell and its instances need to have pins reordered to match the subcircuit definition in the SPICE netlist. Otherwise, when verilog and SPICE netlists are mixed, the order in which the files are read is critical, and failures due to reading out-of-order are very obscure and nearly impossible to debug.
  
• posted: February 3, 2024 at 2:00am     version: 1.5     revision: 266
  Added a piece of code that handles implicit pins in verilog by doing the following: (1) Checking that the parent cell is verilog, (2) only running after the two cells themselves have been compared and matched, then (3) added the missing pin or pins while reordering pins on instances (note: this may not work if the verilog netlist is the first passed to netgen; that case needs to be checked).
  
• posted: January 4, 2024 at 2:00am     version: 1.5     revision: 265
  Corrected two different errors: (1) When a comment line follows a ".subckt" line, and the comment line is empty or all whitespace, then the following line would be ignored. This condition appears to be very specific and was solved simply by detecting it and handling it. (2) Occasionally the "M" parameter of a subcircuit will be recorded as type double, and this was not being anticipated by the code that checks if "M=1" matches a corresponding entry with no "M" parameter. Simple fix to check the condition where the "M" parameter is type double.
  
• posted: December 4, 2023 at 2:00am     version: 1.5     revision: 264
  Corrected the LDDL_FLAGS setting for Mac OS, which is to replace "-flat_namespace -undefined suppress -noprebind" to "-undefined dynamic_lookup" which is what was done in magic, which has a similar structure to netgen.
  
• posted: November 21, 2023 at 2:00am     version: 1.5     revision: 263
  Corrected an error in parallel_sort and series_sort that does not move to the start index before relinking the sorted entries. That will cause properties to be lost whenever the start index is greater than zero. Not sure why this hasn't been caught previously, or whether other errors are involved here.
  
• posted: October 28, 2023 at 2:00am     version: 1.5     revision: 262
  Corrected an error in the previous commit which made primitive devices from a .prm file into class "subckt" when they should be class "module" (because they are primitives). Otherwise, netgen will crash when attempting to flatten them.
  Added code to the netgen Tcl startup script to grab the PDK_ROOT variable used with open_pdks, so that PDK references can be made independent of the local filesystem.
  Also: Corrected an error in the flattening routine that will cause the "flatten" command to crash if there are black-box subcircuits in the netlist.
  
• posted: October 27, 2023 at 2:00am     version: 1.5     revision: 261
  Added support for converting a SPICE file to a SIM file simulatable with IRSIM including recent changes made to support multiple device types using the subcircuit "x" component type. This requires reading in a .prm file, which incidentally can be used with any SPICE file to inform netgen of the specific component type of any model defined as a subcircuit.
  One correction to the last commit, to ensure that subcircuits which are MOSFETs are output into the .sim file in correct G-D-S-B order.
  
• posted: October 23, 2023 at 2:00am     version: 1.5     revision: 260
  Corrected the code from version 258 which was supposed to handle the removal of zero-valued devices between ports on the top level (from version 254 they are ignored for levels under the top to prevent port order from getting scrambled). An invalid check was being made to determine if the cells being compared were the top of the compare queue. This has been fixed.
  
• posted: October 4, 2023 at 2:00am     version: 1.5     revision: 259
  Corrected an issue where a mismatch in property type (e.g., string vs. integer) will cause a segfault. Not sure if type promotion is needed at that point because the failing case was a syntax error that caused a double value to be interpreted as a string because it could not be cast into a numeric form.
  
• posted: September 5, 2023 at 2:00am     version: 1.5     revision: 258
  Made two changes to the verilog token parsing in netfile.c in response to Mitch Bailey's github issue #82:
  Modified the handling of zero-valued resistors and voltage sources so that they are *not* removed to make a better match if they are shorting across two ports. If removed, then the port lists will get screwed up. It is better to let the subcircuits fail matching. Then, after the mismatched subcircuits are flattened, if the zero- valued resistor or voltage source no longer connects two ports, it can be safely removed to make a better match.
  Also: One minor change to the previous commit: The check for shorting devices between two ports is ignored for top-level cells, because the scrambled ports won't affect anything in that case, and the error will be reported as a port error, as it should.
  
• posted: September 2, 2023 at 2:00am     version: 1.5     revision: 257
  Modified some of the verilog read-in code to avoid a segmentation fault that would happen if the verilog had illegal syntax of a misspelled net name (although normally netgen is expected not to have to check the verilog for syntax, and there are probably many such cases of netgen failing to handle incorrect verilog and then crashing as a result).
  Removed a block of ill-considered code that moves pins together when they are shorted, because doing so is scrambling the pin order of cells with respect to the instance calls to the cell. Not sure if there is any code that relies on shorted pins being adjacent, though.
  
• posted: August 28, 2023 at 2:00am     version: 1.5     revision: 256
  Updated the config.guess and config.sub files; the newer ones support, among other things, RISC-V.
  
• posted: July 12, 2023 at 2:00am     version: 1.5     revision: 255
  Corrected part of the MatchPins() routine so that the JSON output tracks the output printed to stdout when matching pins. One section of this subroutine used the wrong pointers when writing to the Tcl list (for eventual JSON output) which was the fundamental error. Beyond that, the "debug" case (if used) would fail to run some of the matching code, and the "no matching pin" case needed to be handled for the Tcl list output. Now the terminal output, terminal debug output, and Tcl list output should all be in agreement on the pin lists.
  
• posted: June 13, 2023 at 2:00am     version: 1.5     revision: 254
  Corrected an issue with shorted ports. When shorted ports are connected only to ports and not to any devices, then they do not show up in NodeClasses() and so pass through most of the checks in MatchPins(). A separate correspondence check is needed to make sure that the same shorted ports appear in both netlists.
  
• posted: April 15, 2023 at 2:00am     version: 1.5     revision: 253
  Corrected a problem in the flattening routine, which was a missing method for flattening a subcircuit with property M != 1.
  
• posted: April 14, 2023 at 2:00am     version: 1.5     revision: 252
  Corrected the node merging around zero-volt voltage sources and zero-ohm resistors so that if one of the nodes being merged is a port, it is preferred over the other.
  
• posted: March 30, 2023 at 2:00am     version: 1.5     revision: 251
  Added a missing check for using a verilog macro definition as an array delimeter for an instance array in verilog.
  Added support for simple forms of for() loops in generate blocks. This is done by treating the loop variable as a temporary parameter that is valid only inside the loop, and changing the parameter value on each loop iteration. The file stream position is used to iterate the loop with calls to fseek() and ftell(), so that the input tokenizer continues to work within loops.
  Also: Corrected an error in order-of-precedence of arithmetic operators, ensuring that, e.g., in (a)*b+c, (a)*b gets evaluated before b+c.
  
• posted: March 8, 2023 at 2:00am     version: 1.5     revision: 250
  Changed what was a not-very-well thought out behavior: On being passed an invalid setup file, the netgen "lvs" script uses a trivial default setup and issues no error or warning. Replaced this behavior with an error message and a hard stop.
  Slightly modified the fix from the last commit to allow an empty string for the setup file to be the "trivial default" previously used in case of the setup file not being found. Put a newline around the setup file messages so that they stand out from the rest of the initial output information.
  
• posted: March 7, 2023 at 2:00am     version: 1.5     revision: 249
  Modified code from EquivalenceClasses() that forces the two cells to have unique class hashes. This has the problem that it prevents comparing N-to-1 cells because declaring X->X1 as equivalent breaks the original name equivalence of X->X. The new implementation adds the switch "-unique" to preserve the original behavior. Otherwise, the class hashes are made the same as the 2nd cell passed to the command, and it is the responsibility of the person running LVS to ensure that this is done in the correct direction.
  
• posted: March 5, 2023 at 2:00am     version: 1.5     revision: 248
  Corrected the wrong order of arguments in an strncpy() command that was introduced in a recent pull request, as pointed out by Mitch Bailey in github issue #72.
  
• posted: March 1, 2023 at 2:00am     version: 1.5     revision: 247
  Patches for Clang
  Updated version and fixed a redundant include statement after merging pull request #71 from Donn.
  
• posted: February 28, 2023 at 2:00am     version: 1.5     revision: 246
  Relaxed the prohibition on ((S != 1) && (M != 1)) in device network parallel/series networks. Instead, added a global option with command "property tolerance strict|relaxed" to reinstate the original (strict) behavior on demand, while relaxing it by default. This allows certain series/parallel networks to match numerically even though the schematic netlist may have combined individual devices.
  
• posted: February 25, 2023 at 2:00am     version: 1.5     revision: 245
  Removed X11 definitions from the configuration when compiling with Tcl, since Tk is launched independently through the console script and nothing inside of netgen itself involves graphics. This prevents netgenexec from linking to Tk and X11 libraries.
  
• posted: December 20, 2022 at 2:00am     version: 1.5     revision: 244
  Modified netgen output to not print information about combining individual components in parallel and series as it reduces the networks. This information is available in total in the cell summary.
  
• posted: December 16, 2022 at 2:00am     version: 1.5     revision: 243
  (1) Fixed the series sorting, which needed to be modified to match the parallel sorting routine. This fixes occasional property errors with series-connected devices such as resistors. (2) Added a method to associate properties with specific pins when pins are permutable. This allows netgen to properly check a value like source/drain area when the definition of source and drain has changed due to permutation of the device. (3) Added a "property" command extension "associate" to associate a property with a pin, for use with the method described in (2).
  
• posted: November 17, 2022 at 2:00am     version: 1.5     revision: 242
  Corrected a badly implemented routine that can cause very long run-times on large projects where a lot of cells need to be deleted.
  
• posted: November 5, 2022 at 2:00am     version: 1.5     revision: 241
  Found an error in property matching causing weird errors in the LVS result. The property matching was failing to match (M=1) to (M!=1) if M was not registered as a property name (which it often isn't). This would allow devices with different numbers of instances in parallel to be put in the same matching group, which then could later identify as a mismatch if the instances were checked in a different order.
  Additional correction to the property match subroutine to better check instances with permutable pins when checking parallelized instances with disconnected pins vs. mutually connected pins.
  
• posted: November 3, 2022 at 2:00am     version: 1.5     revision: 240
  Prevented checks from automatically treating two empty cells as black boxes. The check was supposed to check that both empty cells really are black box entries.
  
• posted: November 2, 2022 at 2:00am     version: 1.5     revision: 239
  parameterized string length and increased to 256
  Updated version to go along with pull request #67 from Mitch Bailey.
  Also: Implemented the change from pull request #65 from Mitch Bailey (slightly altered to put the inexpensive flag checks before the more expensive string match).
  
• posted: November 1, 2022 at 2:00am     version: 1.5     revision: 238
  Fixed an error that prints bogus property mismatch errors when netgen is supposed to be checking properties for symmetry sorting, but not reporting anything. This causes mysterious property mismatch errors that don't actually exist to show up in the output.
  
• posted: October 30, 2022 at 2:00am     version: 1.5     revision: 237
  Corrected a problem that is very similar to the last issue, which is that when the "class ignore" command is used, then ports of a parent cell need to be checked for being disconnected if they connect only to ports of an ignored/deleted child cell.
  
• posted: October 26, 2022 at 2:00am     version: 1.5     revision: 236
  Corrected an issue with "flatten": If a cell has disconnected ports, then flattening instances of that cell can cause a port of the parent cell connected to the disconnected port of the child cell to itself become disconnected. If the parent port is not changed to show the disconnected state, then pin mismatch can occur if the netlist being matched didn't have the same flattened subcell. This condition is now detected and handled correctly.
  
• posted: October 25, 2022 at 2:00am     version: 1.5     revision: 235
  Fix for an error causing a segfault. This does not fix the underlying issue (which needs to be investigated), but it does prevent netgen from crashing when it encounters it (netgen will generate an erro message instead).
  
• posted: October 1, 2022 at 2:00am     version: 1.5     revision: 234
  Revert "Part 2 of folding in Mitch Bailey's code. This part is a
  Re-applied the modifications of revisions 231 and 232, and updated the version to revision 234.
  
• posted: September 24, 2022 at 2:00am     version: 1.5     revision: 233
  Restore matching circuits if one is empty (but only if pins match).
  Version updated along with the merge of pull request #62 from Mitch Bailey.
  
• posted: September 18, 2022 at 2:00am     version: 1.5     revision: 232
  Handled backslash-escapes (convert "\" to "\\") when writing pins to the JSON format file (since JSON does not allow single backslash characters. Previously nets had been handled correctly, but not pins. Resolves github issue tracker Issue #60 from Proppy.
  
• posted: September 17, 2022 at 2:00am     version: 1.5     revision: 231
  Added a missing block of code from Mitch Bailey's version that fails to handle a topology match with a pin mismatch situation.
  
• posted: September 16, 2022 at 2:00am     version: 1.5     revision: 230
  Part 2 of folding in Mitch Bailey's code. This part is a significant overhaul of the MatchPins() code, and better handles issues with pins disconnected from nets and removes cases in which proxy pins are incorrectly generated.
  
• posted: September 14, 2022 at 2:00am     version: 1.5     revision: 229
  Start of merging Mitch Bailey's code changes from github pull request #59 ("Pin match"). Because the pull request has rather sweeping modifications, I am doing this in two steps. The change that most breaks with existing comparison methods is in the PinMatch() routine in netcmp.c, where the method of generating proxy pins has been removed. There are specific cases for which the proxy pin method exists, although these were coping with issues arising from extraction in magic which have been dealt with to some extend. Possibly the proxy pin method is no longer needed. So the PinMatch() changes will be done in a second commit where it's easier to revert or modify the changes without affecting the modifications from this commit.
  
• posted: September 13, 2022 at 2:00am     version: 1.5     revision: 228
  Modified behavior for the "-noflatten" option on LVS: Added a command option "flatten prohibit" (or "flatten deny") to prevent a subcell from being flattened at any time during the compare process. Previously, the "-noflatten" option for the "lvs" script had been used to prevent flattening during initial pre-match, but if the circuit passed the prematch phase and subcells were mismatched, they would be flattened regardless of whether or not they were listed by the "-noflatten" option. This also codifies a way to prevent subcells from being flattened in the setup file rather than in the "lvs" command line. Also: Found and fixed a bug that prevents the use of "-noflatten=" with a cell name or list of cell names instead of a filename.
  
• posted: June 28, 2022 at 2:00am     version: 1.5     revision: 227
  Yesterday's commit surfaced two errors in series; this fixes the second one of them, which is a failure to change CurrentTail when an extra (implicit) pin was added to the last component in the current cell, resulting in the failure of Node() to add the new no-connect node, which instead overwrites the pin just created.
  
• posted: June 27, 2022 at 2:00am     version: 1.5     revision: 226
  Corrected a prematch issue that will flatten a cell on one side even when the opposing netlist has a black-box entry for the same cell. The black-box entry can't be flattened, so this just results in the cell mysteriously disappearing from one side.
  Corrected an error in reworking verilog instances to add pins that were implicit in the first instances but made explicit in a later one. If more than one such implicit pin was handled for the same cell, then the pin count would become wrong and rather unpredictable behavior results.
  
• posted: June 15, 2022 at 2:00am     version: 1.5     revision: 224
  Corrected an error in the last commit which can cause the pin enumeration in MatchPins() to overflow the cover() array and cause a segmentation fault.
  
• posted: June 13, 2022 at 2:00am     version: 1.5     revision: 223
  Made minor changes to MatchPins() to handle multiple pins connected to a single net (as can be done with assignments in verilog or with zero-voltage sources or zero-value resistors in SPICE). Corrected an error in the SPICE netlist reader that prevented the proper use of zero-voltage sources as net splitters.
  
• posted: June 9, 2022 at 2:00am     version: 1.5     revision: 222
  Corrected the parsing of verilog netlists to use the right delimiter set when parsing pin names (the correct delimiter set was used in one place but not in another). Extended the pin matching to include the minor hack of ignoring the backslash before backslash-escaped verilog names when there is otherwise no exact match, since many tools convert verilog to SPICE by removing the backslash and trailing space. This avoids pin mismatches in a known set of use cases.
  
• posted: April 16, 2022 at 2:00am     version: 1.5     revision: 221
  Extended the method created in the last commit so that it properly handles both operator order of precedence and parenthetical groups including nested groups.
  Corrected an error in the verilog parser that incorrectly handles the syntax "assign a = b" when both a and b are vectors (but no vector delimiters appear in the assignment).
  
• posted: April 15, 2022 at 2:00am     version: 1.5     revision: 220
  Extended the verilog parsing to parse definitions such that nested definitions are handled correctly. Also: Added code to evaluate simple expressions for array bounds. Previously the parser could handle a value followed by "+" or "-" and a constant. Now it can handle all basic arithmetic.
  
• posted: January 17, 2022 at 3:00am     version: 1.5     revision: 219
  Implemented a change to the way that netgen generates the subcircuit summary, so that the summary lists the total number of devices as well as the number of devices after parallel optimization, in the form "device_name (M->N)", where "M" is the total number of devices, and "N" is the number of devices after parallel combination. This makes the output somewhat more meaningful to the end user. Implementation as discussed in github issue #47.
  Implemented another change discussed in netgen github issue #47 by Anton Blanchard, which prevents the double-loop in the PropertyOptimize() routine from continuing the outer loop if all devices in the run have already been merged.
  
• posted: January 16, 2022 at 3:00am     version: 1.5     revision: 218
  Modified the parallel combination code so that properties of parallel devices are prepended rather than appended, which avoids having to search for the end of what may be a rapidly increasing linked list of properties. This reduces the amount of time spent in the parallel combination code. Thanks to Anton Blanchard for pointing out this inefficiency.
  
• posted: January 1, 2022 at 3:00am     version: 1.5     revision: 217
  Merged changes from github issue #45 from Mitch Bailey. These changes speed up the time needed to flatten an instance, and add clarity to the output by specifying the file number for each cell name being modified during the pre-match stage.
  Modified two print statements to change "%s(%d)" to "%s (%d)" as is my typographic preference.
  
• posted: December 31, 2021 at 3:00am     version: 1.5     revision: 216
  Removed lvs_manager.py, which is a derived file and should not have ended up in the repository, as pointed out by Mitch Bailey in github issue #44. Added lvs_manager.py to .gitignore to prevent that from happening again in the future.
  
• posted: December 30, 2021 at 3:00am     version: 1.5     revision: 215
  Corrected a problem that stems from code that was deprecated and marked as unneeded, so I simply removed the code rather than debug the issue, which was that buses got the delimeters erased for checking but never put back again. Also: Modified the verilog reading code so that if an empty set "()" is given for a pin, then the initial proxy, which is a single net with the name prefix "_noconnect_", can be promoted to a bus if further processing reveals it to be a bus and not a single-bit signal.
  
• posted: December 27, 2021 at 3:00am     version: 1.5     revision: 214
  Corrected a place in the verilog read routine where ob->next is used when ob may be NULL. Added a check in front for ob == NULL. Also: Changed the disconnected node alert so that it does not mention nodes marked "port_mismatch_error". These are disconnected by definition, will show up in the pin list, and printing them as "disconnected pins" is just confusing to the end user.
  
• posted: December 20, 2021 at 3:00am     version: 1.5     revision: 213
  Made a correction to the last commit. The "FlattenUnmatched()" routine does not have an exact equivalent in PrematchLists() and needs to be run beforehand. This fix keeps FlattenUnmatched() from being run on all cells at the beginning and restricts it to being run on the contents of individual cells during matching, after checking if either of the cells is a black-box. Avoiding flattening contents of one side when the other is a black-box (or simply doesn't contain any subcircuits or devices) prevents unnecessary flattening of cells that will never get compared.
  Corrected the last commit (again) because FlattenUnmatched() should not be called after CreateTwoLists(). CreateTwoLists() was being called in one case only to print the contents of the cells, so that part was pulled out into a separate routine.
  
• posted: December 16, 2021 at 3:00am     version: 1.5     revision: 212
  Removed the call to FlattenUnmatched() in CreateCompareQueue(). The FlattenUnmatched() is inefficient compared to just letting the PrematchLists() routine handle flattening of unmatched instances.
  
• posted: December 8, 2021 at 3:00am     version: 1.5     revision: 211
  Added sorting of the output lines for items which match both name and contents (previously wasn't done), and also added sorting for items with non-matching names which have only one item in the group for each circuit (so they must be matching in some sense). This makes the output a bit more readable without re-enabling the compute-intensive sorting method for non-matching entries.
  Modified the output of "debug on" mode to print the instance name for each connection in the dump of incorrect nets. This is definitely critical to finding local swapping errors, and needs to be incorporated into the non-debug mode, preferably as part of the JSON file dump. But that's for later.
  
• posted: November 18, 2021 at 3:00am     version: 1.5     revision: 210
  fix wrong 'hash' being linked in + C99 compat
  remove
  Also: revert removal of superfluous 'extern'
  Also: Updated version to go along with the merge of pull request #39 from Kamyar Mohajerani, with a few minor edits such as renaming my_hash to hashcase, as a better counterpoint to "hashnocase".
  
• posted: November 12, 2021 at 3:00am     version: 1.5     revision: 209
  Corrected the "format" command, which failed to return TCL_OK after executing the command with non-zero options.
  
• posted: October 30, 2021 at 3:00am     version: 1.5     revision: 208
  Cosmetic report changes.
  Updated version to go along with the merge of pull request #37 from Mitch Bailey.
  
• posted: October 29, 2021 at 3:00am     version: 1.5     revision: 207
  When comparing instance counts to determine is flattening makes a better match, flatten cells that have no instances in common. Display a screen message to indicate a re-compare afterr flattening.
  Updated version to go along with the merge of pull request #36 from Mitch Bailey.
  
• posted: October 24, 2021 at 3:00am     version: 1.5     revision: 206
  Revert "Made a correction to the flattening code, removed a duplicate
  Revert "Minor syntactical editing of pull request #33, and updated version
  Also: Revert "Flatten unmatched cells that don't contain instances from the other file.
  Also: Revert "Remove disconnected ports after flattening.
  Also: After reverting back to before pull request #33, updated the version and re-applied the fixes from issue #34.
  
• posted: October 16, 2021 at 3:00am     version: 1.5     revision: 205
  Made a correction to the flattening code, removed a duplicate print statement, and clarified the messages about non-matching circuits at the end, all of them suggestions made by Mitch Bailey (see issue #34 on github).
  
• posted: October 15, 2021 at 3:00am     version: 1.5     revision: 204
  Remove disconnected ports after flattening.
  Flatten unmatched cells that don't contain instances from the other file.
  Also: Minor syntactical editing of pull request #33, and updated version to go along with the merge of the pull request (from Mitch Bailey).
  
• posted: October 6, 2021 at 3:00am     version: 1.5     revision: 203
  Added MacOS (Big Sur) installation instructions.
  Updated version to go along with merge of pull request #32 from Harald Pretl.
  
• posted: September 8, 2021 at 3:00am     version: 1.5     revision: 202
  Reduce and clarify debugging message. Add missing new line to "Flattening non-matched subcircuits.
  Added missing newlines Print debug message every 100 lines
  Also: Changed debug print increment from 100 -> 10000.
  Also: Removed debugging statement.
  Also: Updated version to go along with the merge of pull request #31 from Mitch Bailey.
  
• posted: August 30, 2021 at 3:00am     version: 1.5     revision: 201
  Updated the vezzal docker image version for CI.
  
• posted: August 28, 2021 at 1:15pm     version: 1.5     revision: 200
  Corrected the badge link at the top of README.md to point to my own repository instead of a fork.
  
• posted: August 6, 2021 at 11:38am     version: 1.5     revision: 199
  Updated VERSION as a forced change to check continuous integration on github.
  
• posted: August 6, 2021 at 11:24am     version: 1.5     revision: 198
  Create main.yml
  Update main.yml
  Also: Update main.yml
  Also: Update README.md
  Also: Updated VERSION to go along with the merge of pull request #27 from Sai Charan. Subsequent mirror pushes to github should trigger the continuous integration.
  
• posted: July 30, 2021 at 3:00am     version: 1.5     revision: 197
  Corrected the Makefile in the python directory to set the lvs_manager.py script to be executable, or else "netgen -gui" will not work.
  
• posted: July 16, 2021 at 3:00am     version: 1.5     revision: 196
  Corrected an error in "series_sort" that will overwrite memory randomly if combining series devices that do not have an "S" property (which is the typical case). This will normally result in a crash.
  
• posted: July 12, 2021 at 3:00am     version: 1.5     revision: 195
  A previous attempt (in revision 193) to make the "lvs" script stop saying that pins were mismatched when pin matching was never run accidentally resulted in pin matching not being applied to black-box entries. This has been corrected.
  Correction to the verilog parser to recognize modifiers such as "~", "!", or "-" in front of variable names in a pin list that would render the module behavioral verilog.
  Also: Reinstated some code that had been commented out that prints pin information for a non-matching pin in circuit1 and generates a proxy pin in circuit2---there is some case where this is redundant, I think, but I need to find the example.
  
• posted: July 11, 2021 at 3:00am     version: 1.5     revision: 194
  Corrected the pin matching so that it runs the same loop on unmatched pins on non-black-boxed circuits as it does not black-boxed circuits, but specifically looking for pins that are disconnected on both sides, since those do not appear in the node list and are not otherwise handled. Otherwise, disconnected pins will appear to have disappeared from the first netlist.
  Modified the handling of missing pins (again) such that netgen continues to allow missing pins to match unconnected pins, but *only* on subcircuits below the top level. This essentially forces layouts to separate merged pins with metal resistors, although there should be an option in magic's ext2spice routine that allows "equiv" statements, when declaring equivalence of two ports, to be replaced by a zero volt source or zero ohm ideal resistor.
  
• posted: July 9, 2021 at 3:00am     version: 1.5     revision: 193
  Corrected an error that crept into the netgen.tcl script that causes the "failed pin matching" error message to appear for cells mismatching topology (in which case pin matching is never done).
  
• posted: July 3, 2021 at 3:00am     version: 1.5     revision: 192
  Corrected an error in a recent update that handles the case where a final parallel or series combination needs to be done but there are still multiple property records. The multiplier was being incorrectly applied twice, causing an automatic mismatch in parameter values.
  
• posted: June 26, 2021 at 3:00am     version: 1.5     revision: 191
  Corrected MatchPins so that it returns an error code of 0 when pins are swapped, so that if pin names are swapped on the top level, netgen will report this as a final error message. Otherwise, the mismatch is only reported back in the pin list where it is not obvious.
  Made another correction that prevents netgen from truncating the pin list that it prints in the side-by-side element mismatch comparison for an element, when there is no node record associated with the pin connection. This makes the output clearer.
  Also: Corrected an error probably introduced into the code with the handling of multiple devices during flattening, that will skip over a node record at the end of a subcircuit call being flattened and therefore remove it from the netlist.
  
• posted: June 25, 2021 at 3:00am     version: 1.5     revision: 190
  Corrected an error in the "run converge" and "run resolve" methods. The algorithm is to run without exhaustive subdivision until the last step because this is much faster. The final iteration must be run with exhaustive subdivision on, or else it is possible to have cells with swapped pins matching. The routines that resolve automorphisms were setting exhaustive subdivision for the final iteration. But simple "run converge" and "run resolve" were not.
  
• posted: June 19, 2021 at 3:00am     version: 1.5     revision: 189
  Added a missing method from parallel/series matching which is to add properties across multiple property records in the last matching step, if there are still multiple properties and the values can be combined. Previously, netgen had been assuming that there would only be one property record left at this point, which is not true. This shows up particularly for BSIM fingered devices, since "nf" is ignored.
  Corrected an error not checking for running off the end of a list, in code from a recent commit.
  
• posted: June 17, 2021 at 3:00am     version: 1.5     revision: 188
  Corrected an issue with flattening when the instances to be flattened run to the end of the list of circuit elements. Also corrected another issue caused by the flag to denote multiple no-connect pins, which can be on an instance pin and so cannot share the data from the instance record.
  Corrected a minor issue that cropped up today in which the search for file extensions is greedy and picks the first matching extension starting at the front of the string, such that, e.g., "file.ext.spice" is interpreted as a ".ext" file and not a ".spice" file.
  
• posted: June 15, 2021 at 3:00am     version: 1.5     revision: 187
  Corrected an issue that was caused by introducing a type of parallel device with one or more no-connect pins. The flag that indicates a no-connect pin was checked incorrectly, potentially causing obscure and misleading property mismatch messages to be generated.
  
• posted: June 13, 2021 at 3:00am     version: 1.5     revision: 186
  Modified the way flattening is done to account for multiple property records, which were being ignored. This really only applies to parallel subcircuits being flattened. To flatten correctly requires that any circuit with N property records must be flattened into the parent at least N times. To do: Must look for M > 1 records in the properties and flatten (M - 1) additional times.
  Correction to previous commit (failed to link to last pointer after processing properties during flattening).
  
• posted: June 10, 2021 at 3:00am     version: 1.5     revision: 185
  Corrected a minor error where the property mismatch check outputs an error message while doing a non-final iteration, where all output is supposed to be suppressed.
  Modified the JSON output so that missing pins which do not match unconnected pins in the other netlist are marked as "(no pin)" rather than "(no matching pin)". This allows a script parsint the JSON file (e.g., count_lvs.py from qflow) to distinguish between a real pin error and one that can be ignored.
  
• posted: June 9, 2021 at 3:00am     version: 1.5     revision: 184
  Messed up basic pin comparison between black-box vs. non-black-box subcircuit situations in the last commit. This commit fixes it.
  Modified MatchPins so that pin mismatches on nets that are not connected to anything are once again ignored (the prior commit to prevent netgen from not reporting swapped pins as an error overcorrected).
  
• posted: June 4, 2021 at 3:00am     version: 1.5     revision: 183
  Finally corrected the issue with pins being able to be swapped without netgen noticing---this behavior got broken by an exception for "black box" circuits, but failed to check if the circuit really was marked as a "black box" or not. Fixing that revealed another issue with verilog implicit pins. Both issues have now been corrected.
  
• posted: May 31, 2021 at 3:00am     version: 1.5     revision: 182
  Made a number of usability corrections to the python GUI for netgen. More work will be done later. Also: Removed the derived file lvs_manager.py from the repository, and modified the Makefile to remove it as part of "make clean".
  
• posted: May 29, 2021 at 3:00am     version: 1.5     revision: 181
  The previous method change for sorting to accommodate capacitors and other devices that do not have a "critical property" that determines which properties can add together was flawed and messed up the sorting of devices like transistors and resistors that do have a critical property. Reworked the sorting order so that it makes sense for both situations.
  
• posted: May 27, 2021 at 3:00am     version: 1.5     revision: 180
  Corrected an issue with swapped arguments to PromoteProperty(). Also corrected a superficial issue with an attempt to print out an instance name that doesn't exist. There is an underlying bug here related to cells that have no pins and/or no contents which has not been debugged. The fix just keeps netgen from segfaulting.
  
• posted: May 26, 2021 at 3:00am     version: 1.5     revision: 179
  Added one modification that automatically ignores any cell that has no pins at all. This overrides the default behavior of treating empty cells as "black-box" entries, and avoids attempts to compare cells like logo artwork.
  
• posted: May 25, 2021 at 3:00am     version: 1.5     revision: 178
  Fixed a bad assumption; PropertyOptimize allows devices with different additive properties (like transistor width) to combine; this is totally wrong and may have been left over from code written before the routine was split into simple combinations (add similar devices) and agressive combinations (e.g., add widths together).
  
• posted: May 20, 2021 at 3:00am     version: 1.5     revision: 177
  Corrected an error found in ResolveAutomorphsByProperty which would cause inexplicable output in case of a property error by showing a netlist topography error instead of a property error (but the output shows that the netlists match, and there is no reporting of any property errors). This error was discovered while implementing a better sorting method for parallel combination. The improved method sorts on two properties rather than one, and so should not fall into the error where, say, devices are sorted on W but have different L for a device like a capacitor where no "critical" property is specified (and other similar cases, although that is a common one).
  Added support for expression parameters to be added to a device class during setup, for the purpose of generating some derived value that is used for merging and sorting, such as area = l*w. Note that this likely needs adjusting so that the expression is evaluated but not replaced for the purpose of sorting, since the values to the parameter may change after parallel and series merging.
  Also: Changed a comment in the code that no longer applies after the last modification.
  
• posted: May 14, 2021 at 3:00am     version: 1.5     revision: 176
  Modified the behavior of the parallel combination of devices with "similar no connect" pins so that it is not done on top-level netlists. This is mainly to deal with the problem where connections that would normally be pins (but may have, for example, been connected to a voltage source in a schematic that was deleted because it was not a netlistable device) are treated as no-connects. The parallel combination of devices with similar no-connects can then differ between netlists that differ in describing transistors as fingered vs. individual devices. This is an obscure case, but the output of netgen then becomes not only wrong but difficult to understand what happened, so it is better to avoid.
  Updated the versio with the last commit.
  
• posted: May 4, 2021 at 3:00am     version: 1.5     revision: 175
  Corrected an error in checking merge flags when doing sorting of parallel and series devices. This was a fairly major error undermining the property sorting (the case where the same number of devices are in parallel in both circuits and need to be sorted by, e.g., width, prior to checking for matches).
  
• posted: May 2, 2021 at 3:00am     version: 1.5     revision: 174
  Missed a corner case in the series combination code where a device has been shuffled to the beginning of the cell, which requires different handling.
  Updated version.
  
• posted: March 20, 2021 at 3:00am     version: 1.5     revision: 173
  Modified the "-noflatten" command option to "lvs" so that it can be given a filename as a value in addition to being passed a list of cells directly.
  Slight modification to print the list of cells being forced to match for both the filename option and immediate list.
  Also: Modified the "flatten" command to allow class "module" to be flattened. This is marginally useful---since the "module" class is a black box, it is essentially the same as using the "ignore" command.
  
• posted: March 18, 2021 at 3:00am     version: 1.5     revision: 172
  Corrected a statement related to proxy pins that can cause a segfault condition.
  
• posted: March 6, 2021 at 3:00am     version: 1.5     revision: 171
  Modifed the handling of parallelized no-connects so that the behavior can be turned on or off from the setup using "property parallel open" to allow parallelizing devices with no-connect pins vs. "property parallel connected" to only allow parallelizing of devices with all pins connected.
  Corrected an error in the code that handles no-connects as valid pins for enabling parallel combinations, which could cause a crash. Added a "-force" option to "equate pins" to allow pins to be matched even on subcircuits that did not correctly match; this was done in conjuction with an extra option to the "lvs" command "-noflatten=" to pass a list of cellname to not be flattened even if they do not match. This is generally discouraged, as it prevents netgen from resolving differences between layout and schematic hierarchy, but it can be useful for checking that the hierarchy above a certain cell is correct, given that if a subcell is really unmatched, then its errors will keep propagating up the top level, making additional errors hard to diagnose.
  Also: First and simplest (but most effective) cut at aligning the two sides of the output when presenting side-by-side results. This matches up net or device names within a partition. Where net or device names match, the contents are also aligned on either side. I attempted to also do a "best match" of contents between sides, but as this involves a lot of analyzing the contents, it is very computationally expensive, and so the code has been disabled. It could be added back in as an option. There are also various ways to optimize it for speed.
  Also: Corrected some pointer-to-int and int-to-pointer conversions to keep the compiler happy.
  
• posted: March 3, 2021 at 3:00am     version: 1.5     revision: 170
  Remove netgen.{sh,tcl} and add them to .gitignore
  Updating VERSION with pull request #18 on github.
  Also: Corrected an error from yesterday's commit; the test case for parallel combinations with disconnected nodes works with the error, but in general it won't.
  Also: Resolved the case mentioned in a prior commit where the case of N devices in parallel with unconnected pins would be confused with N devices in parallel with those pins all tied together. This is treated as a property error.
  Also: Corrected a missing variable in a print statement in the SPICE read routine that can cause a segfault.
  
• posted: March 2, 2021 at 3:00am     version: 1.5     revision: 169
  Modified the parallel combination code to treat cells as equivalently parallel if the same pins are no-connects. These were previously not treated as parallel because each no-connect has a unique node number, and cells were only considered as parallel if all pins connected to the same node numbers. This avoids issues with long-running symmetry breaking on standard cell designs due to cells like antenna taps or any cell that is placed without connecting it up. To do: This makes indistinguishable certain cases, e.g., N cells in circuit 1 with pin X open vs. N cells in circuit 2 with pin X all tied together. This could be caught during property matching.
  Removed the code for fast symmetry breaking, as it has been found to generate incorrect results on occasion. The method to parallelize cells with the same no-connect pins should avoid the worst-case symmetry breaking that was previously plaguing the LVS of large standard-cell layouts.
  Also: Removed the symmetry breaking option from the scripted "lvs" command.
  
• posted: February 25, 2021 at 3:00am     version: 1.5     revision: 168
  Corrected an error that (in a rare circumstance) can cause netgen to go into an infinite loop and fill memory until it crashes, due to a complete pin mismatch between devices causing one device to have its pins removed and replaced with proxy pins.
  
• posted: February 17, 2021 at 3:00am     version: 1.5     revision: 167
  Found a chokepoint in FlattenInstancesOf that was unnecessary as it was running through the entire object linked list to find the predecessor of a record that it had already found. Solved by simply keeping track of the predecessor record.
  
• posted: February 10, 2021 at 3:00am     version: 1.5     revision: 166
  Added a zero-value current source to the zero-valued devices handled by the pre-matching method. The current source is treated like the others except that it forms an open circuit rather than a short.
  Added handling of control blocks (.CONTROL ... .ENDC) in ngspice- format files to the SPICE parser, so that netgen can be run directly on a testbench file and not generate errors due to statements in the control block.
  
• posted: January 22, 2021 at 3:00am     version: 1.5     revision: 165
  Modified netcmp.c "addproxies" routine to not get confused by cells with no pins marked with a "(no pins)" placeholder. Otherwise it goes into an infinite loop and eats up memory until it crashes.
  Updated VERSION.
  
• posted: January 18, 2021 at 3:00am     version: 1.5     revision: 164
  Fix missing prototype for ReadVerilogFile function
  Updated VERSION with the merge of pull request #15 from Alessandro de Laurenzis.
  
• posted: January 17, 2021 at 3:00am     version: 1.5     revision: 163
  Increase OBJHASHSIZE
  Updated VERSION to go along with the merge of pull request #14 from Anton Blanchard.
  
• posted: January 9, 2021 at 3:00am     version: 1.5     revision: 162
  Corrected a potential crash condition while doing series combination.
  
• posted: December 21, 2020 at 3:00am     version: 1.5     revision: 161
  Corrected a problem causing a segfault during a property record copy if the property record does not have a model.class record (should it always?).
  
• posted: December 16, 2020 at 3:00am     version: 1.5     revision: 160
  Added patch from Mitch Bailey which sorts the objects in a verilog file input so that pins occur first before nodes, as they do in a SPICE netlist. Certain parts of the comparison code depend on pins being first in the netlist, and reordering them when reading input is easier than rewriting the rest of the code.
  
• posted: December 6, 2020 at 3:00am     version: 1.5     revision: 159
  Removed the netgen.sh and netgen.tcl scripts from the repository, which are generated by ./configure and should not be in the repo.
  Updated VERSION with the commit.
  
• posted: December 4, 2020 at 3:00am     version: 1.5     revision: 158
  Rework configure script so exit code works.
  Fix configure script to not clobber CFLAGS.
  Also: Updated version to go along with pull request merge from github.
  
• posted: October 9, 2020 at 3:00am     version: 1.5     revision: 157
  Found a counterexample which shows that the fast symmetry breaking introduced in revision 150 can result in an incorrect result reporting a bad match where the match is actually good (as proven by running the full symmetry breaking on the same netlist). Because the fast symmetry breaking is orders of magnitude faster for large circuits, and because the false positive result appears to be rare, I have introduced a command "symmetry" to switch methods between fast and full. So fast symmetry breaking can be run unless the result fails on symmetry breaking, in which case the method can be switched to full to see if the problem is a false positive or not. This is not an ideal solution, and some investigation is needed to determine if there is a way to apply fast symmetry breaking without encountering a false positive error.
  Added a "-full" switch to the scripted "lvs" command that switches to the old symmetry breaking method (see previous commit message).
  
• posted: October 8, 2020 at 3:00am     version: 1.5     revision: 156
  Corrected problems with the port count routine not being specified with the file number, so that it can get confused between libraries. Also made a fix to coerce one cell class to be forced to be the same in both circuits under some circumstances.
  
• posted: August 9, 2020 at 3:01am     version: 1.5     revision: 155
  Found examples where the automated "pin matching" algorithm causes the top level circuits to be declared matching with no errors even though the pins do not match. "proxy pins" are fine for subcells to detect cases where one subcell has an unused pin and the matching subcell does not declare it, but that should not be allowed on the top level, as it cannot be known whether the pin is unused or not.
  
• posted: August 4, 2020 at 3:00am     version: 1.5     revision: 154
  Corrected the left-hand side assignment for "assign" statements and corrected the error statement so that it refers both to the (corrected) left-hand side and also the portion of the right-hand side that cannot be parsed as structural verilog.
  Corrected a bounds check on sub-arrays inside bundles, that prevents the bundle from being parsed correctly when any sub-array is only one bit wide.
  
• posted: August 1, 2020 at 3:00am     version: 1.5     revision: 153
  Tracked down and fixed problems with implicit pins in verilog (pins that are not declared in the verilog netlist because they don't connect to anything, and their presence is not required by verilog syntax) and the printing of proxy pins created to act as placeholders for those implicit pins. Also removed the pinting of the "disconnected pin" messages for black-box modules (since by definition they have disconnected pins, because black-box modules have no contents).
  Corrected the PropertyMatch() routine; previously the symmetry breaking by property was only matching properties between circuits but not within the same circuit, which is needed for correct symmetry breaking. But the PropertyMatch() routine assumed that it is passed one item from each circuit, leading to a segfault when running the symmetry breaking within a single circuit. This has been fixed.
  
• posted: July 31, 2020 at 3:00am     version: 1.5     revision: 152
  Corrected one logical error in netcmp.c from the last commit, discovered and fixed by Ahmed Ghazy.
  Updated the version to force the tarball and github mirror.
  Also: Modified the ResolveAutomorphisms() routine once again, to break symmetry of all elements in all symmetric partitions, rather than (as previously done) all elements in each partition, before re- running iterations to convergence. This solves the problem of having a very large number of partitions with a few elements each taking a long time to run.
  Also: Made several corrections to handling of proxy pins when matching black-box circuits, especially those coming from verilog netlists where a pin does not need to be declared and is implicitly floating. This prevents the need to have an explicit black-box entry for any verilog module that may have an instance that does not declare all the pin connections. Also corrected an error which causes mysterious failures if a verilog netlist is read before a SPICE netlist, because the former gets hashed case-sensitive and the latter changes the hashing to case-insensitive. Modified to force the SPICE netlist to be treated case-sensitive, which may cause errors, but is consistent with the reverse order handling, and doesn't cause unexplained errors.
  
• posted: July 30, 2020 at 3:00am     version: 1.5     revision: 151
  Corrected a problem in ResolveAutomorphsByProperty() that causes long run-times even when there are no properties to check. Corrected a problem with SPICE and verilog netlist reading which arbitrarily replaces file extensions even when a file extension is given, resulting in reading the wrong file.
  Updated version to force the new tarball and github mirror.
  Also: Modified the symmetry breaking routine that arbitrarily resolves automorphisms so that it arbitrarily assigns all pairs from circuit1 and circuit2 at once rather than assigning one pair at a time and rerunning to convergence. I'm not sure of the validity of this, other than that I have never seen a circuit fail to match after resolving automorphisms, leading me to believe that the way the symmetry breaking is done is irrelevant.
  
• posted: July 25, 2020 at 3:00am     version: 1.5     revision: 150
  Corrected the routines DescendCountQueue and DescendCompareQueue to include type CLASS_MODULE in the list of types to descend into, since "module" (black-box) types need to be checked for pin matching even if they have no contents. This allows two verilog netlists to be compared against each other.
  
• posted: July 2, 2020 at 3:00am     version: 1.5     revision: 149
  Corrected an error in bundle assignment that failed to make a copy of the root name of the LHS net, and so would use the last root name copied, which might have belonged to something entirely different, or nothing at all.
  Corrected the verilog parser's behavior with respect to string definitions: Now correctly parses everything from the definition name to the end of line as the definition value. Also: The search for definitions in the body of the text does not reject non-alphanumerics "_" and "$" in the definition name, without which definition names containing those characters will go unrecongized. Have not yet extended this to multi-line definition values.
  Also: Extended the code from the last commit to cover cases in which the definition covers multiple lines; this also is a general handler of the backslash-newline continuation line.
  
• posted: June 17, 2020 at 3:00am     version: 1.5     revision: 148
  Corrected an uninitialized variable error in the verilog reading code that produces a segfault condition.
  Removed a restriction on the "equate pins" command such that pins are matched on circuits that have no elements. This condition does not necessarily indicate an error, and matching pins has no adverse affect (while refusing to match them certainly can).
  Also: Added back a correction that did not get made in this code base and so didn't make it into the commit. Handles implicit pins in verilog.
  
• posted: June 4, 2020 at 3:00am     version: 1.5     revision: 147
  Corrected the verilog parsing (yet again!) so that it does not mistakenly flag bus delimiter characters inside backslash-escaped names when looking for bus delimiters.
  
• posted: March 28, 2020 at 3:00am     version: 1.5     revision: 146
  Corrected handling of wire bundles in the verilog parser.
  Additional corrections; needed to maintain port width in the scan structure because it is used in two different places and would have to run a cost-prohibitive search of the cell's object list. Also, was missing recording a bus input/output signal from an "input" or "output" statement (as opposed to in-line signals in the I/O list).
  Also: Final (I hope) correction to netgen for handling signal wraparound for buses applied to instance arrayes.
  Also: One more bug fix. . . unitialized variable error.
  Also: Some additional changes to better identify behavioral verilog blocks.
  
• posted: March 27, 2020 at 3:00am     version: 1.5     revision: 145
  Changed the default string size for tmpstr in flattenInstancesOf from 200 to 1024. Probably this should be dynamically allocated and expanded as needed, as it is holding names that are of increasing length as a hierarchy is descended and the instance prefixes appended to the name.
  Corrected an error in the verilog read to correctly assign signals to bus pins over an array of instances. Takes care of the three situations where the length of the signal bus equals the number of instances; where the length of the signal bus is a multiple of the number of instances; and where the number of instances is a multiple of the length of the signal bus.
  
• posted: March 11, 2020 at 3:00am     version: 1.5     revision: 144
  Corrected some problems with property matching in netcmp.c. However, I have identified an issue that has not yet been resolved, which is that there can be automorphisms that are potentially broken by property matching. Currently, the automorphisms are arbitrarily resolved, then properties are matched---and may fail accordingly.
  
• posted: March 6, 2020 at 3:00am     version: 1.5     revision: 143
  Corrected error in printing the name of a file when it is not found in an "include" statement in either SPICE or verilog. Modified pin matching behavior to force cells in both netlists to be marked as black-box entries if either one is marked as a black-box entry (this may not be needed, but shouldn't do any harm, either).
  Corrected error in property matching that can cause a segfault.
  
• posted: March 5, 2020 at 3:00am     version: 1.5     revision: 142
  Changed behavior of "equate pins" to detect placeholder cells as a different way of treating "black box" cells. Even when the "-blackbox" option is specified, any cell that has no definition will be treated as a black box. This allows comparison of a black-box netlist against a non-black-box netlist, such as a verilog netlist vs. a SPICE netlist, without forcing the black-box attribute on the SPICE netlist. Then, if the SPICE netlist contains cells without elements such as fill/decap/tap cells, they can be flattened and removed instead of forcing an error or requiring the use of "ignore".
  Corrected problem in flattening code that would attempt to flatten a cell that mismatched by having zero instances. Which fails and repeats indefinitely.
  Also: Corrected the verilog parser to handle backslash-escape notation in instance names, and to ignore bus delimiters inside backslash- escaped names when determining if a net is a bus or not.
  Also: Changed behavior of MatchPins so that disconnected pins that are to be removed because they do not match pins on the other cell being compared, are marked with a different number (-2) than the usual (-1). CleanupPins then only removes those pins that are marked, rather than all disconnected pins.
  Also: Updated VERSION for new tarball.
  
• posted: February 24, 2020 at 5:35pm     version: 1.5     revision: 141
  Corrected Makefile to use -include instead of include on defs.mak so that "make distclean" works.
  Updated VERSION manually; checking regeneration of tarball.
  
• posted: February 24, 2020 at 4:39pm     version: 1.5     revision: 140
  Removed VERSION from .gitignore, and updated VERSION.
  Update for change in ocd git script
  Also: Test update of VERSION.
  
• posted: February 18, 2020 at 3:00am     version: 1.5     revision: 138
  Modified the Makefile per the patch from Charlene at OpenBSD to add GR_LIBS to the list of options to CC, as this apparently prevents problems with older binutils, and should not affect builds otherwise.
  
• posted: February 11, 2020 at 3:00am     version: 1.5     revision: 137
  Based on code from John Wood, added command "netgen::format " to set the output format width, to avoid the fixed column widths of 41 characters which can truncate long strings in the output such as deep cell hierarchies. This command can be placed in the setup script to widen the output columns to accomodate the result (to-do: provide an "auto" mode to automatically determine the best width).
  One additional change to allow a single value to the "format" command to apply to both column widths.
  
• posted: January 30, 2020 at 3:01am     version: 1.5     revision: 136
  Added a distributed install option "--with-distdir=" which replaces "prefix" with the specified path during install, so that netgen can be installed in a separate location to be migrated to the final install location, without appending the entire install path to DESTDIR.
  Corrected configure.in to correctly use withval for setting the with-distdir option.
  Also: One correction to a variable not pointing to the correct distributed install location for --with-distdir.
  
• posted: January 14, 2020 at 3:00am     version: 1.5     revision: 135
  Added handling of backslash characters in instance names in the JSON output. Previously, only net names were checked for backslash characters.
  Changed the behavior with respect to backslashes in the JSON so that they are converted to the double-backslash escape that is the proper JSON syntax for backslashes, instead of being removed, which changes the name and can be confusing.
  
• posted: November 20, 2019 at 3:00am     version: 1.5     revision: 134
  Corrected an error that allows a variable to be used uninitialized in parallel_sort, resulting in a (potentially intermittant) segfault condition.
  
• posted: October 9, 2019 at 3:00am     version: 1.5     revision: 133
  Corrected the verilog parser for handling parameters and parameters with increment/decrement syntax at the end. Also the parser now handles additional keywords associated with behavioral verilog (initial, specify) and flags modules with them as black-box entries.
  
• posted: September 11, 2019 at 3:00am     version: 1.5     revision: 132
  Corrected missing case (greater-than or equal instead of greater than) that affects vectors sliced across instance arrays. Can cause vector numbers to be out-of-bounds if an instance is arrayed but each instance is listed separately.
  
• posted: September 10, 2019 at 3:00am     version: 1.5     revision: 131
  A fairly large refactoring of the conditional handling code in the verilog parser. The parser should now be able to handle any conditionals anywhere in the verilog code. Also a bug was found in the code that handles "a = b" assignments, and corrected.
  Additional fixes to the verilog parser, including handling the inline-I/O syntax with "wire" (e.g., "input wire [3:0] test") and addressed the failure to add buses declared in inline I/O to the list of known buses.
  
• posted: September 9, 2019 at 3:00am     version: 1.5     revision: 130
  Added support in the verilog parser for definitions anywhere in the code using the backtick expression. Also expanded the parsing of "ifdef", "ifndef", and "endif" to include "elsif" and "else". All forms of "if" statements should now be handled, since verilog does not define boolean expressions in ifdef operators like most languages do.
  
• posted: August 20, 2019 at 3:00am     version: 1.5     revision: 129
  Modified the netgen token parser, which (unwisely) is used both for SPICE and verilog, in spite of the syntactical differences, to account for the trick that qflow uses to replace the trailing space in a verilog backslash-escaped name with a second backslash to get a SPICE-compatible name that can be easily converted back to its original verilog name without loss of information. What this means is that verilog can read SPICE files containing verilog names (which is illegal SPICE) and verilog files containing hacked-backslash names (which is illegal verilog). This should be mostly harmless although the wisdom of it is surely questionable.
  
• posted: August 13, 2019 at 3:00am     version: 1.5     revision: 128
  Some corrections and updates to the commit of a few days ago to handle wire bundles in wire assignments and pin connections. Also corrected an error in which a comment after a wire statement causes parsing issues.
  
• posted: August 11, 2019 at 3:00am     version: 1.5     revision: 127
  Expanded the verilog parser to handle most forms of allowable wire and assignment statements in verilog netlists, including assignment of signal bundles. Also corrected handling of signal bundles in pin connections, which had been corrected in qflow's verilog parser but not copied back to netgen. Note that the syntax for signals multiplied N times is still not handled.
  
• posted: August 4, 2019 at 3:00am     version: 1.5     revision: 126
  Updated tkcon.tcl, which was not corrected for a minor problem that affects use with Tcl/Tk 8.6 (text option "-under" not recognized; must be "-underline").
  Added FreeBSD installation comment to README.
  Also: Fixed configure scripts for FreeBSD builds
  Also: Removed generated files and edited .gitignore
  
• posted: July 25, 2019 at 3:00am     version: 1.5     revision: 125
  Corrected a missing "#ifdef TCL_NETGEN" around a Tcl subroutine call, in objlist.c.
  
• posted: July 15, 2019 at 3:00am     version: 1.5     revision: 124
  Removed "makedbh", which was copied from Magic (a long, long time ago) when building out the netgen Makefile, and never removed. The script is very specific to Magic.
  
• posted: July 3, 2019 at 3:00am     version: 1.5     revision: 123
  Corrected a typo that somehow crept into the verilog delimiter set, replacing the semicolon with a colon, which basically hoses the verilog parser.
  
• posted: June 16, 2019 at 3:00am     version: 1.5     revision: 122
  Corrected an error in handling partial buses connected to a full-bus pin in a module instance.
  Corrected an error in the "permute forget" Tcl command option that would attempt to access uninitialized variables, possibly causing a crash.
  Also: Corrected the arguments to the configure script from the top-level wrapper.
  
• posted: June 13, 2019 at 3:00am     version: 1.5     revision: 121
  Corrected error in detecting S and M.
  
• posted: May 18, 2019 at 3:00am     version: 1.5     revision: 120
  Corrected property value merging (again). By the rules of the re-worked property command, "critical" properties must match across devices so that all other properties can be combined as specified (addition, parallel combination, or none). The code was still based on the older notion of the "critical" property being the one to add (and thus preventing multiple properties from being added in different ways). This has now been fixed.
  Further refined the last commit based on the change in definition of a "critical property". This lets a device define multiple critical properties, all of which must match before additive properties can be combined in the same device.
  
• posted: May 7, 2019 at 9:12am     version: 1.5     revision: 119
  Corrected handling of verilog backslash-escaped names in the verilog netlist parser.
  
• posted: January 22, 2019 at 3:00am     version: 1.5     revision: 118
  Update at Mon Jan 21 20:30:40 EST 2019 by tim
  Small typo, large effect; wrong reference to ob1 (instead of ob2) in flatten.c can cause a segfault when analyzing whether flattening cells generates a better circuit match.
  
• posted: January 10, 2019 at 3:00am     version: 1.5     revision: 117
  Update at Wed Jan 9 20:31:54 EST 2019 by tim
  Fairly substantial overhaul of the tokenizing routine to better handle verilog syntax. Also: Added SPICE voltage and current sources as separate classes (as opposed to being converted to subcircuits, which was how they were previously handled). That allowed voltage sources to be checked for zero value and removed by shorting the ends together, as was being done for zero value resistors (note that like zero-value resistors, removal is only done if removing the component makes a better match than leaving it in). In particular, yosys has SPICE netlist output that converts equality assignments ("assign a = b") into zero-value voltage sources, so these components need to be treated as non-physical elements.
  
• posted: November 20, 2018 at 3:00am     version: 1.5     revision: 116
  Update at Mon Nov 19 08:12:57 EST 2018 by tim
  Corrected two instances of missing values on return from a function.
  
• posted: November 19, 2018 at 3:00am     version: 1.5     revision: 115
  Update at Sun Nov 18 13:09:56 EST 2018 by tim
  Extended the series/parallel merging setup commands to include the possibility that a device (e.g., resistor or capacitor) may not be a semiconductor device (in other words, a parasitic or ideal device), and therefore uses "value" but not width and length, and therefore "value" is a critical property to merge both in series and parallel. Corrected the series/parallel network optimization to prevent it from setting both M and S records > 1 on the same device (which is ambiguous). To try to get number of devices to match, where there are both series and parallel devices, they will be merged across the critical property early (before property matching).
  
• posted: November 15, 2018 at 3:00am     version: 1.5     revision: 114
  Update at Wed Nov 14 13:46:12 EST 2018 by tim
  Fixed configure script error that reports python3 as being configured even when it is not found on the system. This was only a reporting error, and had no other repercussions.
  Also: Corrected an error in the handling of node names in verilog that was accidentally erasing array delimiters from node names, a move that surprisingly has no effect at all on LVS until the cell containing the truncated nodes is flattened, at which point it causes odd and confusing behavior that seems to have nothing to do with node names at all.
  
• posted: November 13, 2018 at 3:00am     version: 1.5     revision: 113
  Update at Mon Nov 12 16:33:14 EST 2018 by tim
  Encountered a problem with parsing non-inlined ports of a module and tracked it down to a "to be completed" comment in the source code. So it is now completed.
  
• posted: November 1, 2018 at 3:00am     version: 1.5     revision: 112
  Update at Wed Oct 31 14:05:09 EDT 2018 by tim
  Modified the JSON generation script to backslash-escape backslashes in verilog net names, which are apparently legal in verilog but not in python strings (if not escaped). This is somewhat critical for running the LVS GUI as yosys can generate backslashes in generated net names in the synthesized netlist.
  
• posted: October 30, 2018 at 3:00am     version: 1.5     revision: 111
  Update at Mon Oct 29 15:19:54 EDT 2018 by tim
  Extended the verilog parser to account for the fact that there can be whitespace between a wire/register name and its array delimiter.
  
• posted: October 3, 2018 at 3:00am     version: 1.5     revision: 110
  Update at Tue Oct 2 14:41:38 EDT 2018 by tim
  Removed references to /usr/local/man/man1 and netgen.1, as the netgen.1 man page does not exist. Running mkdirs on the empty directory causes problems with "git rm".
  
• posted: September 27, 2018 at 3:00am     version: 1.5     revision: 109
  Update at Wed Sep 26 10:49:04 EDT 2018 by tim
  Corrected property matching so that properties are promoted to type double before sorting (previously, property promotion was being done after parallel sorting). Also, modified the verilog file reading so that parameters and definitions that are numeric are stored as numeric (not string) properties.
  
• posted: September 25, 2018 at 3:00am     version: 1.5     revision: 108
  Update at Mon Sep 24 15:13:30 EDT 2018 by tim
  Substantially improved verilog parsing (although almost certainly not perfect). Given the complexities of the verilog language, the simple strtok() tokenizer used by the SPICE parser is not sufficient. Wrote a better tokenizer that can distinguish between whitespace and functional tokens like parentheses, semicolons, etc., which are tokens themselves but also token separators.
  
• posted: August 9, 2018 at 3:00am     version: 1.5     revision: 107
  Update at Wed Aug 8 11:28:43 EDT 2018 by tim
  Changed the netgen shell script from "sh" to "bash" due to the presence of one or more bash-isms in the code. Thanks to Sean Cross for the patch.
  
• posted: August 2, 2018 at 3:00am     version: 1.5     revision: 106
  Update at Wed Aug 1 15:44:32 EDT 2018 by tim
  Modified the verilog reading code so that it will automatically determine if a parameter is a floating-point number, integer, or string, and set the parameter accordingly. Found an error in the parameter comparison if the subcircuit definitions don't agree on the type of parameter. Now all values are promoted to a single type based on preference order (double, integer, string). Tested on a verilog file with a primitive device type defined as a module with its properties encoded as parameters. This successfully matched against the SPICE primitive device.
  
• posted: June 26, 2018 at 3:00am     version: 1.5     revision: 105
  Update at Mon Jun 25 21:26:47 EDT 2018 by tim
  Modified the SPICE parser to at least sanely deal with (possibly CDL syntax) parameters that have values which are multi-word and space separated (who the hell comes up with these things?). One can presumably safely assume that additional pin names are not intermixed with parameters, so now if a multi-token parameter value is encountered, the first word is taken as the value and the remaining words are ignored, generating a warning message. Since I have no idea what these values are used for, I cannot say with certainty whether or not this would break LVS, but in the test case given to me, the parameter had no impact on LVS, but was apparently an annotation for the layout editor.
  
• posted: June 18, 2018 at 3:00am     version: 1.5     revision: 104
  Update at Sun Jun 17 15:06:17 EDT 2018 by tim
  Corrected missing tcl.h includes, which are needed in files that call FREE(), since the Tcl/Tk version makes that a macro for the subroutine Tcl_Free(). Thanks to Laurent Charrier for the bug fix.
  
• posted: June 2, 2018 at 3:00am     version: 1.5     revision: 103
  Update at Fri Jun 1 08:47:33 EDT 2018 by tim
  Added a missing top-level clean to the Makefile, which is mainly responsible for removing the log files. Otherwise the log files just keep accumulating output forever.
  
• posted: May 29, 2018 at 3:00am     version: 1.5     revision: 102
  Update at Mon May 28 21:39:11 EDT 2018 by tim
  Removed "Depend" from the .gitignore file, as compilation depends on it and fails the first time if it does not exist, requiring running "make" twice (which is not advertised in the build instructions).
  
• posted: May 24, 2018 at 3:00am     version: 1.5     revision: 101
  Update at Wed May 23 13:05:15 EDT 2018 by tim
  Revised the verilog parser to correctly identify and parse parameters passed to instances, so that these can match critical parameters in the SPICE netlist being compared against.
  
• posted: May 2, 2018 at 3:00am     version: 1.5     revision: 100
  Update at Tue May 1 14:08:16 EDT 2018 by tim
  First pass at incorporating the efabless LVS manager GUI into the netgen distribution. It sort of works, but not quite there yet.
  
• posted: April 27, 2018 at 3:00am     version: 1.5     revision: 99
  Update at Thu Apr 26 08:01:18 EDT 2018 by tim
  Fixed a script error that caused pins not to be reported in the Tcl list and JSON formatted outputs.
  
• posted: April 26, 2018 at 3:00am     version: 1.5     revision: 98
  Update at Wed Apr 25 15:03:16 EDT 2018 by tim
  Expanded the verilog parsing to include simple handling of ifdef, ifndef, endif conditional statements. Pre-define the key "LVS" for use with netgen. Also corrected some problems stemming from the way delimiters are handled and the flexible use of whitespace in verilog.
  
• posted: April 17, 2018 at 3:00am     version: 1.5     revision: 97
  Update at Mon Apr 16 15:43:23 EDT 2018 by tim
  Corrected basic problem with verilog instance pins not needing to be in any specific order since all ports are named. Also corrected problem with pin names not using the same string matching function as used for nets in general (which affects the ability to match against different bus delimiters).
  Also: Corrected the known issue with pin bus index matching that was in the last commit and which was expected to be corrected by this commit.
  
• posted: April 13, 2018 at 3:00am     version: 1.5     revision: 96
  Update at Thu Apr 12 17:13:41 EDT 2018 by tim
  Added new handling for verilog structural netlists, and fixed some problems stemming from comparing a case-sensitive netlist against a case-insensitive one. Verilog netlist reading does not yet have support for macros other than "`include", and it does not yet have support for bit vectors constructed with braces ({}).
  
• posted: April 6, 2018 at 3:00am     version: 1.5     revision: 95
  Update at Thu Apr 5 10:10:44 EDT 2018 by tim
  Discovered a subtle error caused by running a setup script that calls "equate pins". This could fail because the routine that forces uniqueness of pins was being called by the "compare" command but outside of PinMatch. Fixed by duplicating the call to force uniqueness of pins inside the "equate" function. Redundant calls should not matter as uniqueness is resolved on the first call and subsequent calls will need no further action.
  
• posted: March 29, 2018 at 3:00am     version: 1.5     revision: 94
  Update at Wed Mar 28 12:40:15 EDT 2018 by tim
  Corrected a crash condition during pin matching if any subcell has no pins at all.
  
• posted: January 30, 2018 at 3:00am     version: 1.5     revision: 93
  Update at Mon Jan 29 13:26:39 EST 2018 by tim
  Changed behavior of the "lvs" script so that the setup file can be specified as "nosetup" if the "lvs" command is being called interactively from a terminal or as part of a larger script where setup commands have been issued prior to running the "lvs" script. Similarly, the log file can be specified as "nolog" to prevent any log file from being generated.
  
• posted: January 27, 2018 at 3:00am     version: 1.5     revision: 92
  Update at Fri Jan 26 11:58:05 EST 2018 by tim
  Corrected a number of function returns, mainly to avoid compile- time warnings and errors. Removed the "-lazy" option from the Tcl load command, which is not needed when the stubs libraries are compiled in correctly, and which causes issues on some systems (e.g., Mac OS). Thanks to Matt Guthaus for the patch.
  
• posted: December 17, 2017 at 3:00am     version: 1.5     revision: 91
  Corrected an issue in which netgen would attempt to find a file from a ".include" line by trying alternate extensions. This should be discouraged, as it happened that a file included "name.defparams", a file that didn't exist, and instead of calling out the missing file, it recast it to "name.spice" and caused it to drop into an infinite loop. Oops.
  Also: Update at Thu Dec 14 21:50:32 EST 2017 by tim
  Also: Merge branch 'master' into work
  
• posted: December 8, 2017 at 3:00am     version: 1.5     revision: 90
  Corrected Tcl list output (and, by consequence, the JSON file output) to include pin information (missing "-list" argument to the "equate pins" command).
  Also: Update at Thu Dec 7 08:46:40 EST 2017 by tim
  Also: Merge branch 'master' into work
  
• posted: October 11, 2017 at 3:00am     version: 1.5     revision: 88
  Corrected two errors in the serial combine function, one which misses a device if it has been already moved due to earlier merging in the serial combine routine, and runs off the end of the list; the other if the pin check routine falls on the last device in the list, leading to an incorrect check for a record where there is only a NULL.
  Also: Update at Tue Oct 10 22:25:49 EDT 2017 by tim
  Also: Merge branch 'master' into work
  
• posted: August 25, 2017 at 3:00am     version: 1.5     revision: 87
  Prevented a crash condition in the error case in which ports are unordered at the time of reaching reorderpins(). Pins will be ordered arbitrarily (in the order of appearance in the linked list), but netgen will not crash.
  Also: Update at Thu Aug 24 09:51:44 EDT 2017 by tim
  Also: Merge branch 'master' into work
  
• posted: August 11, 2017 at 3:00am     version: 1.5     revision: 86
  Update at Thu Aug 10 22:41:12 EDT 2017 by tim
  
• posted: August 10, 2017 at 3:00am     version: 1.5     revision: 85
  Update at Wed Aug 9 09:04:43 EDT 2017 by tim
  
• posted: June 23, 2017 at 3:00am     version: 1.5     revision: 84
  Corrected coding error in tilde expansion of .include filenames.
  Also: Update at Thu Jun 22 08:12:59 EDT 2017 by tim
  Also: Merge branch 'master' into work
  
• posted: June 21, 2017 at 3:00am     version: 1.5     revision: 83
  Implemented better black-box handling. Netlist with "stub" entries for subcircuits (.subckt ... .ends pair with cellname and pin names and pin order, but no contents) are automatically treated as black- box circuits if found and if the "-blackbox" option is passed to the "lvs" (scripted) command. The "equate pins" command can be used outside of a comparison to force two circuits (black-box or otherwise) to be matched by pin name (if not a black-box circuit, then this is a provisional name match, as a circuit comparison will order based on connectivity first, not pin names). So two sets of black-box circuit libraries can be used as long as their pin names match. One hack added to ignore the "!" at the end of global names when comparing pin names for matching. Otherwise, pin names must compare by case-insensitive string match.
  Also: Update at Tue Jun 20 22:55:24 EDT 2017 by tim
  Also: Merge branch 'master' into work
  
• posted: June 20, 2017 at 3:00am     version: 1.5     revision: 82
  Added tilde expansion handling for .INCLUDE statements to the SPICE netlist read routine.
  Also: Update at Mon Jun 19 12:39:00 EDT 2017 by tim
  Also: Merge branch 'master' into work
  Also: New command option "model blackbox on|off" makes "readnet spice" treat empty subcircuits as blackbox cells automatically without requiring specific callse to "model blackbox" for each. Enabled in LVS script by giving option "-blackbox" at the end of the LVS command.
  Also: Fixed the "cells -all" command so that it now matches the documentation, and behaves as intended, which is that "-all" is not a standalone option but is itself an optional qualifier to the "cells " command. So the options are "cells " and "cells -all ".
  Also: Finally reworked "cells" command behavior into something consistent.
  Also: Corrected the "property parallel none" command option so that it gets applied properly to all existing cells (as well as all future cells, but normally the former is applicable in a setup file for LVS).
  
• posted: June 19, 2017 at 3:00am     version: 1.5     revision: 81
  Update to add "property parallel none" command option.
  Also: Update at Sun Jun 18 22:48:11 EDT 2017 by tim
  Also: Merge branch 'master' into work
  
• posted: May 16, 2017 at 3:00am     version: 1.5     revision: 80
  Corrected the same error as a few commits back that causes a message about property errors to show up, not due to property errors, but due to proxy pins being inserted in the middle of a device record. However, the first one was fixed for the case of proxy pins being added to circuit 1, but the same fix was not made for the opposite case of proxy pins being added to circuit 2. This commit corrects that omission.
  Also: Update at Mon May 15 16:31:00 EDT 2017 by tim
  Also: Merge branch 'master' into work
  
• posted: May 9, 2017 at 3:00am     version: 1.5     revision: 79
  Corrected rare case where a cell that is flattened is the first instance in a cell, and is empty, and causes the cell contents to be nulled out.
  Also: Update at Mon May 8 20:56:58 EDT 2017 by tim
  Also: Merge branch 'master' into work
  Also: Removed old comment from code referring to the development state.
  
• posted: May 6, 2017 at 3:00am     version: 1.5     revision: 78
  Corrected error in combining property records of serial devices.
  Also: Update at Fri May 5 17:36:29 EDT 2017 by tim
  Also: Merge branch 'master' into work
  Also: Corrected an error placing proxy pins after the first pin of the first object if the (presumably top-level) cell has no pins (top-level cells not in a subcircuit definition satisfy this condition).
  
• posted: April 26, 2017 at 3:00am     version: 1.5     revision: 77
  Corrected the .gitignore file, which was apparently missed when version 1.5 was first created in git.
  Also: Update at Tue Apr 25 08:47:57 EDT 2017 by tim
  Also: Merge branch 'master' into work
  
• posted: March 7, 2017 at 3:00am     version: 1.5     revision: 76
  A few corrections to the JSON format output.
  Also: Update at Mon Mar 6 14:01:25 EST 2017 by tim
  Also: Merge branch 'master' into work
  
• posted: March 4, 2017 at 3:00am     version: 1.5     revision: 75
  Corrected new JSON file output format from netgen.
  Also: Update at Fri Mar 3 09:11:52 EST 2017 by tim
  Also: Merge branch 'master' into work
  
• posted: February 28, 2017 at 3:00am     version: 1.5     revision: 74
  Corrected an error in the property match subroutine that was failing to stop at the end of an instance record without properties, leading to strange errors where netgen declares "There were property errors" but does not print any errors (because there aren't any).
  Also: Update at Mon Feb 27 09:36:52 EST 2017 by tim
  Also: Merge branch 'master' into work
  
• posted: February 9, 2017 at 3:00am     version: 1.5     revision: 73
  Corrected an error where snprintf() was not used when printing formatted side-by-side output, causing a crash for names that exceed the 40-column limit.
  Also: Update at Wed Feb 8 15:16:59 EST 2017 by tim
  Also: Merge branch 'master' into work
  
• posted: January 10, 2017 at 3:00am     version: 1.5     revision: 72
  Finished implementing the Tcl list output format, and added a routine to convert the list output format to a JSON output file, for easy readback, parsing, and display using python.
  Also: Update at Mon Jan 9 12:52:59 EST 2017 by tim
  Also: Merge branch 'master' into work
  Also: Removed backup file for netgen.tcl.in, and made corrections for the output JSON format, which was incorrect when some entries were empty.
  
• posted: January 8, 2017 at 3:00am     version: 1.5     revision: 71
  Fixed a bug in the combine routine that causes a segfault; added preliminary support for a Tcl list output format.
  Also: Update at Sat Jan 7 06:57:25 EST 2017 by tim
  Also: Merge branch 'master' into work
  
• posted: December 13, 2016 at 3:00am     version: 1.5     revision: 70
  Completed the implementation of serial/parallel device network matching.
  Also: Update at Mon Dec 12 11:32:42 EST 2016 by tim
  Also: Merge branch 'master' into work
  Also: Removed backup file.
  Also: Corrected typo with == vs. =
  Also: Correction to device property matching code to fix a problem that caused LVS(A, B) to give different results for property errors than LVS(B, A).
  
• posted: December 8, 2016 at 3:00am     version: 1.5     revision: 69
  Added more handling of serial/parallel device networks, including making any subcircuit serializable by using the new command option "property (device) serial|parallel enable|disable". Note that as of this commit, serial device detection is enabled but serial networks are not collapsed for matching, which will tend to lead to property errors in serial devices until this code is added, which should be in a day or two.
  Also: Update at Wed Dec 7 15:01:55 EST 2016 by tim
  Also: Merge branch 'master' into work
  Also: Several errors in the serial combination code fixed, and then the serial combination routine was disabled so as not to post a non-working version, since the parallel/serial property networks are not analyzed. This should be completed soon.
  Also: Fixed an error that prevented 'circuit1' and 'circuit2' from being used in the general cell name format as advertised (in fact caused a segfault), without which all setup file have to be very circuit- specific.
  
• posted: November 12, 2016 at 3:00am     version: 1.5     revision: 68
  Corrected an error in which property types were not promoted if an instance property did not match the cell property type, as long as the cell property types of the two compared cells matched. Along with a recent change that left "M" as a type double during SPICE netlist read-in, this caused "M" mismatches to be ignored, because the double value was ignored and the integer value was always zero.
  Also: Update at Fri Nov 11 09:52:18 EST 2016 by tim
  Also: Merge branch 'master' into work
  
• posted: October 27, 2016 at 3:00am     version: 1.5     revision: 67
  Disabled the newest unfinished experimental code, which was not supposed to have been pushed to git yet.
  Also: Update at Wed Oct 26 21:21:09 EDT 2016 by tim
  Also: Merge branch 'master' into work
  
• posted: October 26, 2016 at 3:00am     version: 1.5     revision: 66
  Changed behavior of property mismatch reporting. This is to help avoid the problem where non-critical properties cause devices not to match, resulting in apparent mismatches of matched devices. The current behavior now prints a statement about each device. However, the result is still somewhat ambiguous.
  Also: Update at Tue Oct 25 11:29:17 EDT 2016 by tim
  Also: Merge branch 'master' into work
  
• posted: October 25, 2016 at 3:00am     version: 1.5     revision: 65
  Removed all instances of macro INLINE, as this is showing up now as failing on certain compilers. This undoubtedly reflects some change in gcc or the OS setup, but since modern compilers should be able to figure out for themselves when to inline a subroutine (or not), the inline hint is somewhat arcane and unnecessary.
  Also: Update at Mon Oct 24 13:43:29 EDT 2016 by tim
  Also: Merge branch 'master' into work
  
• posted: October 19, 2016 at 3:00am     version: 1.5     revision: 64
  Corrected error in property matching, especially to handle problems with missing properties in instances that prevent matching (underlines need to add the code to apply defaults from the object where these occur).
  Also: Update at Tue Oct 18 09:59:36 EDT 2016 by tim
  Also: Merge branch 'master' into work
  Also: Corrected error that fails to remove property records of any instance that is deleted because it has been ignored with the 'ignore' command.
  Also: Implemented command option 'ignore shorted', same syntax as 'ignore class', but removes instances of the specified class whose pins are shorted together. Currently requires that all pins must be shorted together.
  
• posted: October 18, 2016 at 3:00am     version: 1.5     revision: 63
  Corrected parsing of resistor and capacitor values to include CDL-style expressions as well as numerical values.
  Also: Update at Mon Oct 17 17:47:55 EDT 2016 by tim
  Also: Merge branch 'master' into work
  
• posted: September 21, 2016 at 3:00am     version: 1.5     revision: 62
  First attempt to properly use the Tcl/Tk stubs library feature.
  Also: Update at Tue Sep 20 21:51:09 EDT 2016 by tim
  Also: Merge branch 'master' into work
  
• posted: September 10, 2016 at 3:00am     version: 1.5     revision: 61
  (1) Corrected output of "nodes" command, which was not handling the leading '/' of pin names and therefore failing to print anything; (2) Corrected 'addproxies', which was ending abruptly at the end of a circuit's object list, such that if an instance needing proxy pins added was the last object in the circuit, it would not get the proxy pins added, and therefore would fail LVS.
  Also: Update at Fri Sep 9 09:47:45 EDT 2016 by tim
  Also: Merge branch 'master' into work
  
• posted: September 9, 2016 at 3:00am     version: 1.5     revision: 60
  Corrected error in tclnetgen for command option "property default", which did not return from the command after processing the "default" option.
  Also: Update at Thu Sep 8 22:08:20 EDT 2016 by tim
  Also: Merge branch 'master' into work
  
• posted: July 22, 2016 at 3:00am     version: 1.5     revision: 59
  Updated configure script to extract the paths for the Tcl and Tk lib and include files, so that subsequent checks for those files are not disjoint from the contents of tclConfig.sh and tkConfig.sh.
  Also: Update at Thu Jul 21 11:24:27 EDT 2016 by tim
  Also: Merge branch 'master' into work
  
• posted: July 17, 2016 at 3:00am     version: 1.5     revision: 58
  Corrected use of strdup instead of strsave, which causes a different malloc() to be called and can cause crashes.
  Also: Update at Sat Jul 16 13:52:34 EDT 2016 by tim
  Also: Merge branch 'master' into work
  Also: Added command option "property default" which acts similarly to "permute default" by (1) handling the usual case for MOSFETs (resistors and adding in parallel not yet implemented), and (2) being done automatically when no setup script is specified.
  Also: Implemented critical property combining in parallel for devices such as resistors.
  Also: Added resistors and inductors to the list of devices whose merging properties are defined by "property default".
  
• posted: July 12, 2016 at 3:00am     version: 1.5     revision: 57
  Finished basic implementation of matching device properties to include calculations of effective width due to the addition of width of multiple device instances in parallel. The original behavior of splitting all "M=" devices into individual instances has been effectively inverted, instead combining all parallel devices of the same class into one, with multiple property records for devices with non-matching properties (e.g., width, length, etc.). Property matching combines devices with different "critical properties" (e.g., FET gate width) if these are defined in the setup using the "property merge" command.
  Also: Update at Mon Jul 11 08:49:52 EDT 2016 by tim
  Also: Merge branch 'master' into work
  Also: Removed the deprecated file flatten.c.bak.
  
• posted: June 24, 2016 at 3:00am     version: 1.5     revision: 56
  Overhaul of the hash table method. Original method used global variables to iterate over hash table contents. This led to the inability to nest hash table iterators. Fixed by defining a wrapper structure that holds the actual hash table plus the size and iterator indexes. Not only does this solve the nesting problem, but it also avoids the need to pass the hash table size on every call, and that reduces the number of ways a hash table subroutine can go wrong (e.g., cannot access the table out of bounds simply by passing a size that is larger than was used to initialize the table).
  Also: Update at Thu Jun 23 10:18:47 EDT 2016 by tim
  Also: Merge branch 'master' into work
  Also: Extended the prematching phase to include matching of devices based on properties that can be traded with number of devices, such as MOSFET width, by merging. This initial implementation is somewhat limited, only dealing with properties that merge by summing. Only devices that do not match at all in the other circuit will be considered for merging. The feature includes a command option "property ... merge ..." that allows control over which devices can and cannot be merged.
  
• posted: May 20, 2016 at 3:00am     version: 1.5     revision: 55
  Corrected a previously-working output of a list of cells with property errors at the end of LVS. The result of "verify matching" got overwritten by the result from matching pins, erasing the information about a cell having property errors.
  Also: Update at Thu May 19 16:46:32 EDT 2016 by tim
  Also: Merge branch 'master' into work
  
• posted: May 18, 2016 at 3:00am     version: 1.5     revision: 54
  Prevented error messages about undefined properties for devices.
  Also: Update at Tue May 17 09:05:09 EDT 2016 by tim
  Also: Merge branch 'master' into work
  
• posted: May 17, 2016 at 3:00am     version: 1.5     revision: 53
  Fairly extensive modifications that allow for handling of, and comparisons between, duplicate cells (cells with the same netlist that may have more than one name in a circuit, or which for some reason appear with the same name more than once in a netlist). Added more checks to the list prematching, which prevents various troubles with cells having a mismatched hierarchy. Added a command option to "flatten class" to flatten instances only within a specific cell. Corrected one error in the pin matching routine. Added a check in the pin matching routine to look for pins that have been found to be no-connects after cleaning up the pin lists of the children of that cell.
  Also: Update at Mon May 16 10:55:53 EDT 2016 by tim
  Also: Merge branch 'master' into work
  Also: Added additional diagnostic statements.
  Also: Removed files that should not be in the git repository
  Also: Updated the .gitignore file to avoid the .log and .so files.
  Also: Corrected the "property tolerance" command in tclnetgen, and cleaned up some of the property matching output.
  
• posted: May 6, 2016 at 3:00am     version: 1.5     revision: 52
  Corrected a line in FlattenUnmatched that would cause an infinite loop if attempting to flatten an empty cell.
  Also: Update at Thu May 5 10:12:58 EDT 2016 by tim
  Also: Merge branch 'master' into work
  Also: Fixed a potential crash condition in uniquepins().
  
• posted: March 21, 2016 at 3:00am     version: 1.5     revision: 51
  Corrected handling of name matching so that if the setup file equates class "a" in circuit 1 with class "b" in circuit2, and if circuit 1 has a class called "b" and/or circuit 2 has a class called "a", then both classes are given a new hash to avoid conflicts with the (presumably) unrelated cells of the same name in the other netlist.
  Also: Update at Sun Mar 20 11:44:06 EDT 2016 by tim
  Also: Merge branch 'master' into work
  Also: Additional measure to ensure that name altered to avoid cross- netlist naming conflicts does not also cause a naming conflict.
  Also: Corrected an additional error that let PropertyMatch() be called with arguments swapped with respect to Circuit1, Circuit2 definitions, which are fixed in PropertyMatch().
  Also: Corrected an error causing a segfault on property mismatches where one cell is missing properties (failed to check for a NULL value before checking values internal to the structure that was NULL).
  
• posted: March 17, 2016 at 3:00am     version: 1.5     revision: 50
  Corrected the device pre-matching routine to not segfault when a cell has zero instances in one of the surveyed cells.
  Also: Update at Wed Mar 16 12:06:38 EDT 2016 by tim
  Also: Merge branch 'master' into work
  
• posted: December 8, 2015 at 3:00am     version: 1.5     revision: 49
  Corrected calls from the non-Tcl/Tk version to routines which have been modified in the Tcl/Tk version to take an additional argument for the file number. In the non-Tcl/Tk-compatibility mode, netgen should operate in a backwards-compatibility mode with filenum = -1.
  Also: Update at Mon Dec 7 15:01:41 EST 2015 by tim
  Also: Merge branch 'master' into work
  
• posted: November 16, 2015 at 3:00am     version: 1.5     revision: 48
  Update to configuration script
  Also: Update at Sun Nov 15 16:53:51 EST 2015 by tim
  Also: Merge branch 'master' into work
  
• posted: April 30, 2015 at 3:00am     version: 1.5     revision: 39
  Corrected error with .ext and .sim file reading, in which the (indirect) match and hash functions were undefined.
  Also: Update at Wed Apr 29 17:08:52 EDT 2015 by tim
  Also: Merge branch 'master' into work
  Also: Oops, somehow managed to run qflow in the netgen source directory and it dumped some files there. . .
  
• posted: April 18, 2015 at 3:00am     version: 1.5     revision: 38
  Rewrote the prematch algorithm to accept decomposing a subcircuit if the resulting match is closer than the original match (as opposed to not allowing it to create a mismatch in the opposite direction, even if it's a very small mismatch compared to the original). Doing this led me to discover, more or less by accident, that the original prematch "step 1" of decomposing any subcircuit having no match in the other netlist is subsumed by "step 2", which is better able to determine when decomposing a subcircuit isn't going to be any help at all. This results in fewer circuits being decomposed, and therefore a cleaner/faster compare at the topmost level.
  Also: Update at Fri Apr 17 10:08:50 EDT 2015 by tim
  Also: Merge branch 'master' into work
  
• posted: April 10, 2015 at 3:00am     version: 1.5     revision: 37
  Modified netgen.tcl to add return characters back into lines read from setup.tcl, or else it does not properly parse multi-line commands. Run commands by "uplevel 1", so that they run in the top-level scope, as they would from the Tcl command line. This move brings up the issue that "global" cannot be used without prefixing with "netgen::", which is stated plainly in the netgen output but should really be changed to make the problem go away, by not having a "global" command in netgen. Also: Corrected an error in MatchPins that would miscount pins when ignoring a pin disconnected in both netlists, generally causing a panic in memory allocation down the road.
  Also: Update at Thu Apr 9 20:09:00 EDT 2015 by tim
  Also: Merge branch 'master' into work
  Also: Revised the setup file evaluation to operate within the netgen namespace, to avoid gotchas with the command "global", on advice from Risto. Seems to work properly.
  
• posted: April 9, 2015 at 3:00am     version: 1.5     revision: 36
  Binary input detector. . .
  Also: Update at Wed Apr 8 09:31:29 EDT 2015 by tim
  Also: Merge branch 'master' into work
  Also: Rewrote parts of the spice parser and expression parser until they pass the "/dev/urandom" test; the parser is now quite robust. Kept the code that stops on apparent binary input files, as it is more practical to stop processing rather than to assume that there is a netlist in there somewhere. . .
  Also: Modified setup file parsing to evaluate one line at a time, and catch errors and report warnings about such errors without causing a halt to the LVS process. This replaces the specific "(ingored)" messages for commands like "permute", which now return error results. The consequences of this change are (1) you can type complete gibberish into the setup file, like "Hey, this is an error", and it will just spit out a warning; (2) you can't do loops, define procedures, etc., within the setup file, as it is now restricted to one command per line. However, you can get around this by adding a one-line "source " to parse a file with multi-line commands or structures.
  Also: On a tip from Risto, modifed the setup file parsing using "info complete" to allow the parser to handle arbitrary Tcl scripts without complaint.
  
• posted: April 8, 2015 at 3:00am     version: 1.5     revision: 35
  Corrected the expression parsing, which was incorrectly freeing the memory for a string that was never allocated, if the expression reduces to a single string.
  Also: Update at Tue Apr 7 08:30:19 EDT 2015 by tim
  Also: Merge branch 'master' into work
  Also: Corrected the property error reporting to properly report when two properties cannot be matched because they cannot be resolved to the same type (e.g., both type double, integer, or string), and to avoid promoting a type that is not really promotable (e.g., turning a fractional value into an integer).
  Also: Corrected an error in inductor parsing that caused the inductor value to be taken as a model name, for inductors without models. Added additional support for other minor non-physical SPICE types such as voltage and current sources. They are modeled as black boxes, meaning that they only match pins but do not compare properties unless the properties are specifically called out in the setup file.
  Also: Added inductors to the list of devices with default permutations.
  
• posted: April 7, 2015 at 3:00am     version: 1.5     revision: 34
  Corrected parsing of numbers and expressions to disambiguate the use of +,-, and "e" as an exponent vs. use as arithmetic and variable names.
  Also: Update at Mon Apr 6 20:18:45 EDT 2015 by tim
  Also: Merge branch 'master' into work
  
• posted: April 6, 2015 at 3:00am     version: 1.5     revision: 33
  Start of coding for handling of device combinations. Added command "combine", similar to "permute", with defaults defined, and the capability to override from the setup file. Currently has no function other than to set flags in the device record.
  Also: Update at Sun Apr 5 21:04:52 EDT 2015 by tim
  Also: Merge branch 'master' into work
  
• posted: April 5, 2015 at 3:00am     version: 1.5     revision: 32
  Added a new set of subroutines to handle the arithmetic expressions that appear in CDL netlists, taking ".PARAM" statements for global values, plus substituting in the value of properties passed to instances from a subcircuit. It does not yet detect multiple uses of subcircuits with different sets of parameters. However, the code as it is now will handle most simple applications of parameter passing.
  Also: Update at Sat Apr 4 21:44:08 EDT 2015 by tim
  Also: Merge branch 'master' into work
  
• posted: April 4, 2015 at 3:00am     version: 1.5     revision: 31
  Corrected error in property matching that would break on the first instance property not listed in the cell master, and ignore the rest of the properties. Added a hash table for handling parameters in spice files, but this feature is preliminary, and currently does nothing of interest.
  Also: Update at Fri Apr 3 09:36:52 EDT 2015 by tim
  Also: Merge branch 'master' into work
  
• posted: April 3, 2015 at 3:00am     version: 1.5     revision: 30
  Fixed a number of errors related to handling the "permute" command, and corrected the common cellname parsing to properly handle the "*" wildcard.
  Also: Update at Thu Apr 2 08:19:36 EDT 2015 by tim
  Also: Merge branch 'master' into work
  Also: Corrected property matching so that (1) if one cell has properties that are not required and the other cell has no properties, no error will be raised, and (2) failure to match due to missing (required) properties is posted as a separate error message.
  Also: Slight correction to print the instance name rather than the cell name of the instance missing properties; otherwise it's difficult to track down the offending entry in the netlist.
  Also: Finally got around to cleaning up the "property" command. Command now works correctly with wildcards, like the other commands. Several parsing errors were found and corrected. No attempt yet to extend the command definition beyond what it was; mainly correcting existing errors in the established syntax.
  Also: Corrected log output so that the final tally of property mismatched devices gets copied to the log. Otherwise the log can seem to indicate that everything matched perfectly, when some cells in the hierarchy had property mismatches.
  Also: Corrected erroneous code in "permute forget", referencing a freed pointer.
  Also: Corrected "property tolerance", which was setting an interpreter error result when given a floating-point value.
  
• posted: April 2, 2015 at 3:00am     version: 1.5     revision: 29
  Implemented automorphism resolution by pin matching and property matching. If automorphic groups connect to pins, then the pins are compared by name and the name matching used to sort the automorphisms into unique sets. Then, properties are checked within each automorphic group, and the groups assigned new hash values based on equal numbers of components with matching properties in each circuit. Another match iteration is run following each sort. Remaining automorphic groups are then truly ambiguous, and are resolved arbitrarily.
  Also: Update at Wed Apr 1 11:23:22 EDT 2015 by tim
  Also: Merge branch 'master' into work
  Also: An attempt to clean up the output, preventing tabs from being dropped in the log file, putting the more useful node mismatch in front of the element mismatch, and changing names of various things that seem kind of arcane: element -> device, node -> net, cell -> circuit, automorphism -> symmetry, legal -> matching, illegal -> nonmatching. This should make the output a bit more human-comprehensible.
  Also: Corrected the "permute" command, which was horribly broken. Implemented wildcard filenum on the "permute" command, untested, with hooks in place to extend the wildcard handling to most of the other commands that use the common filename syntax.
  Also: Corrected a few bugs per bugzilla update on bug 10, and added handling of wildcard file number for most of the routines (but not yet including the "property" command).
  Also: Corrected the filenumber return value of the common cellname parser in the case of a single top-level name. Corrected the error setting for "permute" commands that act on non-existent devices. Cleaned up another few minor aspects of the output formatting.
  
• posted: April 1, 2015 at 3:00am     version: 1.5     revision: 28
  Corrected another missing check for a NULL value that causes a segfault when subcircuits have no pins.
  Also: Update at Tue Mar 31 08:03:46 EDT 2015 by tim
  Also: Merge branch 'master' into work
  Also: Missing reset of "haspins" in SPICE file read, caused only the first cell without pins to be seen to be treated as such.
  
• posted: March 31, 2015 at 3:00am     version: 1.5     revision: 27
  Corrected an error that prevents the use of a comment line ('*') in the middle of a series of continuation lines ('+') in a SPICE netlist.
  Also: Update at Mon Mar 30 13:50:01 EDT 2015 by tim
  Also: Merge branch 'master' into work
  Also: Corrected a place where a name was printed just after freeing the memory for it.
  
• posted: March 30, 2015 at 3:00am     version: 1.5     revision: 26
  Corrected one last (I hope. . .) error in the unique-pin resolving subroutine, which required two passes to allow net numbers to be resolved first, before removing any redundant pins; otherwise, the pin numbering gets messed up.
  Also: Update at Sun Mar 29 16:55:42 EDT 2015 by tim
  Also: Merge branch 'master' into work
  Also: Corrected crash condition with missing check for NULL pointer.
  
• posted: March 29, 2015 at 3:00am     version: 1.5     revision: 25
  Corrected crash condition caused by lack of a check for a null value in the pre-match subroutine. Also corrected the unique pins subroutine.
  Also: Update at Sat Mar 28 21:04:00 EDT 2015 by tim
  Also: Merge branch 'master' into work
  
• posted: March 27, 2015 at 3:00am     version: 1.5     revision: 24
  Reworked the "valid_cellname" parse routine (again) so that the names "-circuit1" and "-circuit2" work under all conditions (previously were parsed only when used as individual items, not part of a list pair). Also stopped setting CurrentCell to NULL after ReadSpice(), which allows "-current" to be used as well, after reading in a cell. Need some kind of command or command option to specifically set the current cell, though.
  Also: Update at Thu Mar 26 08:36:18 EDT 2015 by tim
  Also: Merge branch 'master' into work
  Also: Added more to the pre-match survey, allowing cells that have differing numbers of elements in each circuit to be flattened if the matchup of elements will be improved by the flattening. (Still to do: improve matching based on parallel/serial combinations.)
  Also: Added another element-matching routine to look for unmatched resistors of zero length or zero value, and remove them from the netlist while combining the endpoint nodes. This resolves problems where one netlist breaks up nets with fake resistors but the other one doesn't. In order to match zero-value devices, it is the responsibility of the end user to ensure that both netlists define them.
  
• posted: March 26, 2015 at 3:00am     version: 1.5     revision: 23
  Corrected the case of proxy pins for subcircuits which truly have no pins. This is a bit of a hack, but appears to work correctly now in all cases. Cleaned up the IsPort() and IsGlobal() macros at the same time.
  Also: Update at Wed Mar 25 20:43:09 EDT 2015 by tim
  Also: Merge branch 'master' into work
  Also: Created a command option "compare assign " that will assign Circuit1 and Circuit2, without doing anything else, so that the setup file and other commands prior to running a comparison can make use of the "-circuit1" and "-circuit2" names to refer to the two cells.
  
• posted: March 25, 2015 at 3:00am     version: 1.5     revision: 22
  Corrected an egregious error from the last check-in where an accidental "break" got inserted in the "CleanupPins" subroutine, causing complete corruption of the netlists when "reorderpins" was called.
  Also: Update at Tue Mar 24 09:41:28 EDT 2015 by tim
  Also: Merge branch 'master' into work
  Also: Added code to handle the rare case of a cell that has no ports (because it's connections to the parent cell are all through global nodes).
  Also: Reworked the compare & flatten routine so that it is in its own subroutine and not part of CreateTwoLists(). With its own hash table and counts of matching and non-matching instances, it's in a better position to do more complicated matching, combining of devices, etc.
  
• posted: March 24, 2015 at 3:00am     version: 1.5     revision: 21
  Modified the handling of pins such that netlists do not need to be flattened for the simple reason that their pin lists cannot be matched; netgen now adds unconnected dummy nodes to both sides as necessary to make them match. This makes the hierarchical output much cleaner.
  Also: Update at Mon Mar 23 13:19:42 EDT 2015 by tim
  Also: Merge branch 'master' into work
  Also: Added the number of instances flattend when reporting on the flattening of unmatched subcells.
  
• posted: March 21, 2015 at 3:00am     version: 1.5     revision: 20
  Instituted two new procedures: (1) On first comparison, where number of elements are mismatching, a check is made for unmatched subcircuits that can be flattened. There is some issue where only a portion of non-matching circuits are flattened, requiring several passes, but the feature still works. (2) On mismatch of pins due to extra duplicate or unconnected pins on one circuit, the circuits are NOT flattened, but retained with the circuit lacking the extra nodes having those pins replaced with dummy equivalents. This may need more work and is considered tentative at the moment.
  Also: Update at Fri Mar 20 11:08:26 EDT 2015 by tim
  Also: Merge branch 'master' into work
  
• posted: March 19, 2015 at 3:00am     version: 1.5     revision: 19
  Corrected the property check to avoid crashing when a property record exists but contains no properties. It is not yet clear to me how such a record got made, but for now, treating it the same way as having no properties seems reasonable.
  Also: Update at Wed Mar 18 08:31:41 EDT 2015 by tim
  Also: Merge branch 'master' into work
  
• posted: March 18, 2015 at 3:00am     version: 1.5     revision: 18
  Fixed SPICE read-in to handle the case where a "+" continuation line is followed by nothing but whitespace before the next end-of-line. Previously, the end-of-line was being ignored in this case.
  Also: Update at Tue Mar 17 20:46:42 EDT 2015 by tim
  Also: Merge branch 'master' into work
  Also: Encountered a weird error with indexing from Tcl, corrected with an ugly hack. Pin matching during hierarchical comparison is now working again. Cleaned up a few other things, such as cell names not being printed in the status message from "equate pins".
  
• posted: March 16, 2015 at 3:00am     version: 1.5     revision: 17
  Made a few corrections that prevent segfaults when encountering and attempting to match cells with different numbers of pins.
  Also: Update at Sun Mar 15 19:02:27 EDT 2015 by tim
  Also: Merge branch 'master' into work
  
• posted: March 14, 2015 at 3:00am     version: 1.5     revision: 16
  Corrected configure script for tclConfig.sh and tkConfig.sh search locations.
  Also: Update at Fri Mar 13 20:03:15 EDT 2015 by tim
  Also: Merge branch 'master' into work
  
• posted: March 13, 2015 at 3:00am     version: 1.5     revision: 15
  Corrected output of "tolerance", where double and integer values were swapped, sent to the wrong Tcl command, and therefore mangled into unrecognizable numbers in the output. Also, the output was supposed to be lists of three values. . .
  Also: Update at Thu Mar 12 16:12:37 EDT 2015 by tim
  Also: Merge branch 'master' into work
  
• posted: March 10, 2015 at 3:00am     version: 1.5     revision: 14
  Sweeping changes to the property handling. Previously property handling worked only under the assumption that the two netlists shared the underlying low-level devices. Since netlists are now kept entirely separate and devices are never shared, that assumption is now always false. So the property handling was changed to match between two instances of two cells, not two instances of the same cell. This revision should be considered highly unstable.
  Also: Update at Mon Mar 9 17:31:50 EDT 2015 by tim
  Also: Merge branch 'master' into work
  Also: Implemented one important form of the "equate class" command with pin lists.
  
• posted: March 6, 2015 at 3:00am     version: 1.5     revision: 13
  Added error information dump when executing command-line arguments, in case of an error, so the error isn't just cast into the great void.
  Also: Update at Thu Mar 5 19:35:55 EST 2015 by tim
  Also: Merge branch 'master' into work
  Also: Additional correction to remove added whitespace introduced by the solution found on stackoverflow for parsing command-line arguments.
  Also: Corrected part of the property check, which is to use a symmetric difference for the error computation.
  
• posted: March 5, 2015 at 3:00am     version: 1.5     revision: 12
  Corrected readlib so that libraries read after a netlist read has already created placeholder cells will cause the instance pin names to be updated with the new pin names.
  Also: Update at Wed Mar 4 11:08:38 EST 2015 by tim
  Also: Merge branch 'master' into work
  Also: Implemented part of the "equate classes" command; have not finished the part that allows black-box pins to be named, ordered, and matched. Also cleaned up the few bits of code that spit warnings during the compile, so that the compile is clean.
  Also: Corrected use of quotes when passed both to the console and to the terminal from the command line; for example: netgen lvs map9v3.spice "map9v3_synth.spice map9v3" The new method preserves quotes as a Tcl list in both cases.
  Also: Added a command-line option "-batch" which acts like "-noconsole" except that it executes "quit" after executing the command-line arguments, so that it returns to the terminal prompt instead of the interpreter prompt.
  
• posted: March 4, 2015 at 3:00am     version: 1.5     revision: 11
  First attempt at a "blackbox" method of specifying subcircuits, using the "readlib spice" command. See updated website command syntax description.
  Also: Update at Tue Mar 3 20:48:07 EST 2015 by tim
  Also: Merge branch 'master' into work
  Also: Made one change to set the circuit class appropriately for a black box component. Otherwise, "readlib" would not work right.
  
• posted: March 3, 2015 at 3:00am     version: 1.5     revision: 10
  Corrected the common cellname syntax to include just a file number, as stated in the website command documentation. The file number by itself is equivalent to the top-level filename and top-level cell. Also added a command "canonical" to return a canonical form of a 2-item list {cellname file_number} for any valid cellname input. This is used by the "lvs" procedure to take the common cellname syntax as input. However, the common cellname syntax is only valid for files that have been read in, so the original restricted case of {filename cellname} is required when using the "lvs" command for a database that has not yet been read in. Also changed the "cells" command so that the option "all" is now "-all", to avoid confusion with a possible cell named "all"; and extended the command to include the option "-top" to print the names of top-level cells.
  Also: Update at Mon Mar 2 09:22:13 EST 2015 by tim
  Also: Merge branch 'master' into work
  Also: And once more corrected the cellname processing so that keywords "-circuit1", "-circuit2", and "-current" are parsed properly. It is possible that "-current" is not usable, but then, it's not a necessity.
  
• posted: March 1, 2015 at 3:00am     version: 1.5     revision: 9
  Added quotes around "$@" in the netgen.sh script to preserve whitespace in arguments.
  Also: Update at Sat Feb 28 12:21:08 EST 2015 by tim
  Also: Merge branch 'master' into work
  Also: Fairly sweeping change to make all the commands consistent with respect to the naming of cells. See the updated documentation for syntax details. Due to the previous rampant inconsistency, some of the previous command options have a different syntax, but I have attempted to be as liberal as possible in the naming convention, so breaking of backwards compatibility is minimized.
  
• posted: February 28, 2015 at 3:00am     version: 1.5     revision: 8
  Cleaned up handling of the console, such that batch mode works with the "-noconsole" switch, as it normally would. Redundant checks for the console were removed.
  Also: Update at Fri Feb 27 13:18:12 EST 2015 by tim
  Also: Merge branch 'master' into work
  Also: Removed some diagnostic text that got left behind. . .
  Also: Corrected a bad error where the "ignore" command could delete anything in the object list between the cell being ignored and the next cell; sometimes this would include top-level nodes and other vitally important things.
  
• posted: February 24, 2015 at 3:00am     version: 1.5     revision: 7
  Corrected behavior of the tkcon console, (1) so that on "quit", netgen calls the tkcon exit routine, so that tkcon will clean up after itself and save its history file, and (2) renaming the history file ".netgen_tkcon_hst", so that it will not interfere with the history file from other tools using tkcon.tcl.
  Also: Update at Mon Feb 23 21:02:43 EST 2015 by tim
  Also: Merge branch 'master' into work
  
• posted: December 8, 2014 at 3:00am     version: 1.5     revision: 6
  Generate error message for cells that do not have pins, instead of crashing. Unfortunately, the database only lists pins (and properties), so that even though a cell with no pins (e.g., all connections are globals) is theoretically legal, it cannot be represented in netgen (possibly it could work to add a dummy property?).
  Also: Update at Sun Dec 7 16:40:24 EST 2014 by tim
  Also: Merge branch 'master' into work
  Also: Corrected the flattening routine so that it doesn't crash if attempting to flatten an empty cell.
  Also: Modified the "global" command so that it (normally) acts on a file instead of a cell, although it can also be passed a cellname (in addition to the filename) to change the scope of specific signals in a specific cell (which was how "global" was implemented previously). In addition, any number of signal names to be made global can be put in the same command line.
  Also: Modified the syntax of the "global" command so that it is similar to the "flatten" command syntax.
  
• posted: December 3, 2014 at 3:00am     version: 1.5     revision: 5
  Revised .gitignore so that VERSION is included with a git clone command
  Also: Update at Tue Dec 2 19:13:33 EST 2014 by tim
  Also: Hmmm, that shouldn't happen. . .
  Also: Playing tag with these files. . .
  Also: Still playing file tag. . .
  
• posted: December 2, 2014 at 3:00am     version: 1.5     revision: 4
  Corrected segfault if a nonexistent cell is passed to the "compare" command.
  Also: Minor adjustment to last change, to print the name of the cell that was not found.
  Also: Corrected error with the "lvs" script in which a badly formed regexp allows the first cell name containing the name of the cell being searched for to be returned as a match. Thanks to Risto Bell for the suggested patch.
  
• posted: October 9, 2014 at 3:00am     version: 1.5     revision: 3
  Corrected an error that prevents the "nodes" command from working.
  Also: Update at Wed Oct 8 08:10:54 EDT 2014 by tim
  Also: Merge branch 'master' into work
  Also: Revising .gitignore. . . trying to figure out why files in ".gitignore" are being ignored by git (!)
  Also: .gitignore is now working
  Also: Doing that again; needed directory put in .gitignore
  Also: And once again to fix .gitignore. . .
  Also: Finally should have all the right files in the repository.
  Also: Patched tkcon to be compatible with Tcl/Tk version 8.6.
  Also: Correction to tkcon (fixing a typo!), otherwise bad things happen.
  
• posted: September 24, 2014 at 3:00am     version: 1.5     revision: 2
  Corrected handling of cells that are used before being defined, which got broken by recent code changes.
  Also: Update at Tue Sep 23 20:44:51 EDT 2014 by tim
  Also: Merge branch 'master' into work
  
• posted: Septmber 18, 2014 at 8:23am     version: 1.5     revision: 1
  Attempting to fix website problem caused by not initializing the git tag.
  
• posted: Septmber 17, 2014 at 3:00am     version: 1.5     revision: 0
  Initial check-in of development version 1.5 (unchanged from last revision of 1.4).

Revision information on Netgen 1.4:

Netgen revision history: Version 1.4

• posted: September 10, 2016 at 3:00am     version: 1.4     revision: 81
  Same update as made to netgen-1.5 for using "load -lazy" with Tcl/Tk version 8.6 and up.
  Also: Update at Fri Sep 9 11:09:06 EDT 2016 by tim
  Also: Merge branch 'master' into work
  
• posted: August 12, 2016 at 3:00am     version: 1.4     revision: 80
  Various small corrections to fix the compilation of the non-Tcl/Tk compile, which got broken some time ago.
  Also: Update at Thu Aug 11 15:13:11 EDT 2016 by tim
  Also: Merge branch 'master' into work
  
• posted: July 22, 2016 at 3:00am     version: 1.4     revision: 79
  Updated configure script to extract the paths for the Tcl and Tk lib and include files, so that subsequent checks for those files are not disjoint from the contents of tclConfig.sh and tkConfig.sh.
  Also: Update at Thu Jul 21 11:24:16 EDT 2016 by tim
  Also: Merge branch 'master' into work
  
• posted: October 10, 2015 at 3:00am     version: 1.5     revision: 47
  Updates for cygwin compile.
  Also: Update at Fri Oct 9 12:42:07 EDT 2015 by tim
  Also: Merge branch 'master' into work
  
• posted: September 30, 2015 at 3:00am     version: 1.5     revision: 46
  Corrected syntax information for the "equate" command, and added output text for the "flatten" command when called as a netgen command (as opposed to being called internally to LVS).
  Also: Update at Tue Sep 29 21:51:04 EDT 2015 by tim
  Also: Merge branch 'master' into work
  Also: Corrected an error in which renamed cells do not recalculate the classhash value based on the new name, so they will be treated as equal to the old cell despite the different name.
  Also: Corrected an error in the name-matching of cells. This comparison would look for matching names from the "equate classes" command. However, it failed to do the reverse check, which is to make sure that if no forced match was found for a cell, but there was a name match, that the name-matched cell found is not being forcibly matched to something else.
  
• posted: September 25, 2015 at 3:00am     version: 1.5     revision: 45
  Modified the name-checking when creating compare queues, such that matches explicitly called out in the setup file using "equate classes" will take precedence over same-name matching, instead of the other way around.
  Also: Update at Thu Sep 24 08:26:50 EDT 2015 by tim
  Also: Merge branch 'master' into work
  
• posted: September 1, 2015 at 3:00am     version: 1.5     revision: 44
  Modified the detection of subcircuits such that it does not flag false errors about missing .ENDS statements on the top-level cell at EOF.
  Also: Update at Mon Aug 31 09:34:21 EDT 2015 by tim
  Also: Merge branch 'master' into work
  Also: Corrected an apparently non-functional call to feof(); random end-of-file will now properly terminate instead of re-reading the same line.
  
• posted: August 22, 2015 at 3:00am     version: 1.5     revision: 43
  Added handling for missing ".ends" statement at EOF on a SPICE netlist.
  Also: Update at Fri Aug 21 08:36:17 EDT 2015 by tim
  Also: Merge branch 'master' into work
  
• posted: August 21, 2015 at 3:00am     version: 1.5     revision: 42
  Corrected an infinite loop caused by lack of a return character after ".ends" (seems to be unique to that situation). Also, corrected a segfault caused by a cell definition containing only components that are uninstantiated subcircuits (recently added code makes references to CurrentCell without checking if it exists).
  Also: Update at Thu Aug 20 22:13:39 EDT 2015 by tim
  Also: Merge branch 'master' into work
  Also: Changed output behavior to print a "not checked" message when a cell has no elements and therefore cannot be checked. This message is only printed if "verify only" is used, preventing the message from being output several times. Switched from "stderr" to "stdout", so that it appears after "Result:" in the output, instead of before.
  
• posted: August 11, 2015 at 3:00am     version: 1.5     revision: 41
  Added capability to handle single and double quotes in expressions for parameters.
  Also: Update at Mon Aug 10 12:08:23 EDT 2015 by tim
  Also: Merge branch 'master' into work
  
• posted: August 10, 2015 at 3:00am     version: 1.5     revision: 40
  Added simple code to avoid printing confusing entry when one cell has no pins and the other does; the output was adding an entry attempting to match the "(no pins)" proxy pin.
  Also: Did the same thing for the reverse case.
  
• posted: May 18, 2015 at 3:00am     version: 1.4     revision: 78
  Make update; these files probably should be in .gitignore. . .
  Also: Update at Sun May 17 21:14:46 EDT 2015 by tim
  Also: Merge branch 'master' into work
  
• posted: December 2, 2014 at 3:00am     version: 1.4     revision: 77
  Same change made to version 1.5, to prevent segmentation fault in the case of a bad cell name passed to the "compare" command.
  Also: Update at Mon Dec 1 19:40:19 EST 2014 by tim
  Also: Merge branch 'master' into work
  Also: Corrected error with the "lvs" script in which a badly formed regexp allows the first cell name containing the name of the cell being searched for to be returned as a match. Thanks to Risto Bell for the suggested patch.
  
• posted: October 9, 2014 at 3:00am     version: 1.4     revision: 76
  Corrected an error that prevents the "nodes" command from working.
  Also: Update at Wed Oct 8 08:10:40 EDT 2014 by tim
  Also: Merge branch 'master' into work
  Also: Patched tkcon.tcl to be compatible with Tcl/Tk 8.6
  
• posted: September 24, 2014 at 3:00am     version: 1.4     revision: 75
  Corrected handling of cells that are used before being defined, which got broken by recent code changes.
  Also: Update at Tue Sep 23 20:44:40 EDT 2014 by tim
  Also: Merge branch 'master' into work
  
  0. Nov 24, 2007 at 4:55pm
     Initial check-in of the development distribution. Added automatic test of SPICE file format for "readnet". Added true 4-port and 2-port devices. Added read-in of device properties. Eliminated built-in device classes; all device classes are generated on the fly as the file is read in. For SPICE decks, the device model becomes the device class, so that different device models are compared independently. Added command option "equate classes" to force equivalence between device classes in different circuits. Added "lvs" command option to read in a file of class equivalences.
     
  1. November 26, 2007 at 2:40am
     Made some corrections to avoid confusing properties with nodes of the same name, and to simplify the printout of "contents ". Some simple tests indicate that LVS is working correctly with subcircuit calls (spice X records).
     Also: Corrected an error that causes netgen to hang if "lvs" is given a bad filename.
  2. December 3, 2007 at 2:40am
     Many, many changes. Implemented a set of internally-defined device classes that encompasses pretty much everything (mostly based on SPICE device model types), with some differences such as a distinction between 3- and 4-terminal FETs, and similar items. This internal type also encompasses the original "primitive" flag, in that the internally-defined "subcircuit" device is distinguished as the only non-primitive device. Completely reworked device properties (again) such that only specific properties (e.g., length, width, capacitor and resistor value) are checked, and these are mapped into type double and kept separate from other properties for quick comparison during LVS. Reworked permutation to allow "standard" permutations of source/drain on any device recognized internally as a FET, and endpoints on internally-defined resistor classes, as well as allowing (via script command) permuations to be defined on any pins of any device class. Unfortunately, at the moment, the LVS itself is hosed, as a result of one or more of the above changes. The ability to translate between netlist formats is currently rather limited, the most complete being the reading of SPICE format files and the writing of "sim" format files. Diodes, inductors, and transmission line models are not yet handled in SPICE input.
  3. December 10, 2007 at 2:40am
     More changes. . . changed the "class equivalences" file passed to the "lvs" procedure to a Tcl script setup file, in which class equivalences would be merely one possibility. Permutations as yet cannot be handled here because the permutations currently act upon the netcmp database, and so must be run after the "compare" command; whereas the setup file is executed prior to "compare". Changed the way device properties are handled, so that properties "of interest" to LVS are listed in the cell definition, duplicated in a separate list in each instance, and converted to type double (floating-point) where appropriate. The "properties of interest" are defined at the time the cell definition is created. There needs to be a method to add or subtract the "properties of interest" from the cell definition. Changed the way device models are handled, replacing the "primitive" flag with a value indicating an internal model type. Corrected read/write routines for sim and SPICE files, including correct handling of device models and properties, and unmodeled vs. modeled resistors and capacitors.
     Also: Changed the "permute" command such that it generates a list of pins to permute, but the actual permuation is punted until the element and node classes have been created. This allows the "permute" command to be issued in the setup script.
     Also: Corrected property error checking, which now appears to be correct, at least as verified by running on a few simple examples. Added the capability to specify the degree to which values are required to match (the "slop"), although for now this is set to the default value of 1%, and there is no way to change it (eventually a command will be added to manage property comparison).
     Also: Updated the TO_DO list.
     Also: A couple more corrections to property checks, to make sure that cells are considered matching if their classes are marked as corresponding.
     Also: Added a few corrections for handling nested spice subcircuit definitions. This allows LVS to run correctly on hierarchically-defined files, although for now only the topmost circuit is checked.
  4. December 29, 2007 at 2:40am
     Corrections that I failed to check into CVS last time. In particular, the malloc/free routines are all now correctly assigned to Tcl equivalents.
  5. December 30, 2007 at 2:40am
     Correction in property-checking code to prevent crashes when no properties are specified (namely, on the last device in the list).
  6. December 31, 2007 at 2:40am
     Basic hierarchical LVS has been implemented. However, a lot of cleanup is needed with regard to the output it produces!
  7. March 10, 2008 at 2:40am
     Corrected an error that causes netgen to announce property errors when there are no properties (this will happen on the last device in the netlist, and shows up when the order of the last device is different in the two netlists).
  8. May 23, 2008 at 2:40am
     2008-05-22 17:20 tim Corrected the "package require -exact Tk" problem in tkcon.tcl, which has already been corrected in the magic and IRSIM distributions. The fix is necessary to run the Tcl/Tk-based version with Tcl/Tk version 8.5.
  9. July 7, 2008 at 2:40am
     2008-07-06 11:24 tim Added /usr/share/tcltk to the search path for Tcl and Tk in the configure script, to conform to recent distributions of Ubuntu Linux.
  10. May 21, 2009 at 2:40am
      2009-05-20 08:56 tim Corrected an error found by Kan Chu in which a spice instance name followed immediately by a continuation line is not parsed correctly (the continuation line "+" is passed on as the first pin connection).
  11. May 25, 2009 at 2:40am
      2009-05-24 17:46 tim Corrected the SPICE read functions to (1) correctly handle the "+" continuation line character, and (2) handle carriage-return-linefeed characters from DOS-style text files.
  12. July 28, 2009 at 2:40am
      2009-07-27 06:47 tim Corrected SPICE read-in of semiconductor resistors and capacitors, which should not have a value in front of the model name.
      Also: Additional correction, due to the fact that the syntax of the semiconductor resistor and capacitor models in the standard SPICE documentation conflicts with the example provided underneath. Is the device value mandatory, optional, or prohibited?
  13. August 28, 2010 at 2:40am
      2010-08-27 18:01 tim Numerous changes supporting hierarchical LVS and the ability to read in files with subcells of the same name and keep them distinct. Also, added the ability to compare subcells of files from the "LVS" command, which avoids problems when one or both files come from "library" type GDS files without a top-level cell.
  14. December 21, 2010 at 2:40am
      2010-12-20 17:15 tim Major changes to support hierarchical LVS. Finally encoded routines to sort out port ordering between the schematic and layout circuits. Many issues still to be resolved, but netgen has now successfully run LVS on a magic-extracted hierarchical SPICE deck vs. an xcircuit-generated (schematic capture) hierarchical SPICE deck. Much hand-editing was required. Should resolve these issues over the next several weeks.
  15. December 24, 2010 at 2:40am
      Updated compare routines to ignore disconnected nodes in either circuit's netlist. Also: Modified the SPICE read routine to rename instance pin references after read-in when the instance was called before the cell was defined.
  16. May 26, 2011 at 2:40am
      Corrected an error that generated record 'x' into the output for all device types unknown to the .sim format (fallout from experimental handling of subcircuits in .sim).
      Also: Correction to prevent segfaults on encountering unknown device models.
      
  17. May 29, 2011 at 2:40am
      Corrected a non-initialized variable which causes known model types such as "diode" in a spice file to be overwritten with a subcircuit class, causing confusion with the hierarchical LVS.
      Also: Update at Sat May 28 06:19:36 PDT 2011 by tim
      Also: Merge branch 'master' into work
      
  18. May 30, 2011 at 2:40am
      Updated netgen-1.4 to my most recent development fixes/additions, a number of which had not been committed.
      Also: Update at Sun May 29 12:10:13 PDT 2011 by tim
      Also: Merge branch 'master' into work
      
  19. June 10, 2011 at 2:40am
      Script files regenerated from sources. Changes in this commit are probably not meaningful.
      Also: Update at Thu Jun 9 07:05:10 PDT 2011 by tim
      Also: Modified .gitignore to avoid creating a new revision for changes to logfiles and regenerated script files.
      Also: Merge branch 'master' into work
      
  20. October 27, 2011 at 3:00am
      Correction to netgen-1.4 to deal with undefined "CONST84" in Tcl code.
      Also: Update at Wed Oct 26 05:20:40 PDT 2011 by tim
      Also: Merge branch 'master' into work
      
  21. October 30, 2011 at 3:00am
      Corrected a bad error in sim files where transistor gate and drain are swapped on read-in.
      Also: Update at Sat Oct 29 11:39:14 PDT 2011 by tim
      Also: Merge branch 'master' into work
      Also: Redid the previous correction, changing the arguments in the subroutine instead of in the call, since it's the subroutine argument order that got changed, somehow.
      
  22. March 29, 2012 at 3:00am
      Update at Tue Mar 6 12:30:35 PST 2012 by tim
      Also: Finished a basic implementation of the hierarchical LVS, which unfortunately I earlier abandoned when it was just shy of being completed. The hierarchical LVS now handles pin matching between pairs of cells, so that after the cells are declared matching, the pins are matched up so that the next hierarchical level of comparison will have the same pin order for both. Pins which are not electrically connected are shuffled to the end of the pin list so that cells with phantom pins can be correctly compared.
      Also: Update at Wed Mar 28 10:22:00 EDT 2012 by tim
      Also: Merge branch 'master' into work
      Also: Modifications to enable port sorting in hierarchical LVS. Work in progress.
      
  23. September 2, 2012 at 3:00am
      Corrected an error with a duplicate definition of netgeninterp. Also, changed the configuration script to match the search path used to find Tcl/Tk used in other tools. Finally, corrected an error where the /usr/local/lib/netgen/ directory was not created and would raise an error when trying to copy runtime files into it.
      Also: Update at Sat Sep 1 20:46:33 EDT 2012 by tim
      Also: Merge branch 'master' into work
      
  24. September 4, 2012 at 3:00am
      Corrected the order of libraries in the non-Tcl make of netcomp and friends. Some compiler setups can't take the reverse order, and fail to link properly.
      Also: Update at Mon Sep 3 09:32:25 EDT 2012 by tim
      Also: Merge branch 'master' into work
      
  25. September 7, 2012 at 3:00am
      Another configuration change for Tcl/Tk in lib64
      Also: Update at Thu Sep 6 10:08:28 EDT 2012 by tim
      Also: Merge branch 'master' into work
      Also: Also: Corrected a set of mixed calls to Tcl and C memory free routines.
      
  26. September 10, 2012 at 3:00am
      Update at Sun Sep 9 15:44:10 EDT 2012 by tim
      
  27. September 13, 2012 at 3:00am
      Added more functionality to the hierarchical LVS, which now properly flattens circuits that do not match initially. Also, added parsing for a ".include" record in a SPICE deck.
      Also: Update at Wed Sep 12 13:23:17 EDT 2012 by tim
      Also: Merge branch 'master' into work
      Also: (Small correction to last update)
      
  28. September 16, 2012 at 3:00am
      Finished corrections of the hierarchical LVS, including handling of global nodes through the flattening process.
      Also: Update at Sat Sep 15 13:31:38 EDT 2012 by tim
      Also: Merge branch 'master' into work
      Also: Corrected an issue with CurrentCell being undefined when a .subckt record is found in a SPICE netlist.
      
  29. September 19, 2012 at 3:00am
      Corrected a problem with a mismatch between an allocation using the system strdup() and freed using Tcl_Free().
      Also: Update at Tue Sep 18 10:50:44 EDT 2012 by tim
      Also: Merge branch 'master' into work
      Also: Fixed the fix, which unwisely deleted the much-needed Tcl_Strdup routine, which replaces strsave(), although probably unnecessarily.
      
  30. September 21, 2012 at 3:00am
      Corrected a bug that caused netgen to crash if an attempt was made to include a non-existant file using the ".include" card in a SPICE netlist.
      Also: Update at Thu Sep 20 14:37:35 EDT 2012 by tim
      Also: Merge branch 'master' into work
      
  31. October 1, 2012 at 3:00am
      Correction to parsing of ".global" statement in SPICE netlists: keyword can be followed by multiple arguments, and global node references can be backwards or forwards (i.g., ".global" can be stated after a node has been defined, or before).
      Also: Update at Sun Sep 30 10:20:12 EDT 2012 by tim
      Also: Merge branch 'master' into work
      Also: Corrected an error in the Tcl "lvs" script in which non-matching subcircuits do not report having an error, and do not flatten the subcircuits that do not match. This leaves the possibility that if the top-level circuit has correct connections into the bad subcircuits, the whole netlist will report as matching.
      
  32. October 3, 2012 at 3:00am
      Corrected a typo that crept into the last update. Fixed a rather bad error that failed to clear the current cell when reading a spice file, so the next file could end up believing that the previous file was its "parent".
      Also: Update at Tue Oct 2 16:20:41 EDT 2012 by tim
      Also: Merge branch 'master' into work
      
  33. October 7, 2012 at 3:00am
      Extensive corrections to the LVS comparison code, to properly handle global variables by forcing them to be local at each subcircuit compare, and pass them up to the parent cell as pins. Also created a new side-by-side output format that it much more easily readable than the original output. No attempt is made to organize nets or elements within an illegal fragment, which is next on the to-do list.
      Also: Update at Sat Oct 6 13:28:00 EDT 2012 by tim
      Also: Merge branch 'master' into work
      Also: One additional correction to avoid calling "MatchPins" and printing pin information for top-level cells that have no pin information.
      Also: Correction to SPICE netlist reader: IsPort() should no longer include types GLOBAL and UNIQUEGLOBAL.
      Also: . . . With a little syntactic cleanup
      
  34. October 8, 2012 at 3:00am
      A few more minor enhancements, to handle M=# expressions in capacitors and resistors, to specify the instance name of fundamental devices according to the notation in the SPICE file (instead of renumbering all devices according to an independent internal count), and more cleanly printing property errors.
      Also: Update at Sun Oct 7 11:05:51 EDT 2012 by tim
      Also: Merge branch 'master' into work
      Also: Added handling of the case where automorphisms in a subcell connect to subcell ports. In such cases, the subcell ports should be made permutable, so that the indistinguishable parts of the subcircuit may be called in different orders from the parent cells in each of the two circuits being compared, and they will be matched.
      Also: Since property errors do not prevent netgen from declaring a match, it is easy for property errors to get lost in the middle of the output. So I put some code in to capture the names of cells with property errors and print them out at the end, so that they are easy to see.
      
  35. October 9, 2012 at 3:00am
      Added a side-by-side element count to the comparison output file for each cell. This includes matching up cells in circuit1 vs. circuit2, given that all instances should have been individually LVS'd first, and therefore marked as corresponding.
      Also: Update at Mon Oct 8 12:36:31 EDT 2012 by tim
      Also: Merge branch 'master' into work
      
  36. October 11, 2012 at 3:00am
      Corrected an error in which illegal partitions
      Also: Update at Wed Oct 10 11:21:32 EDT 2012 by tim
      Also: Merge branch 'master' into work
      Also: Additional change to the NodeHash arithmetic causes nodes connected to swapped instances to form illegal node partitions.
      
  37. October 12, 2012 at 3:00am
      Corrected an error that would cause a segfault when reading in a SPICE file having no top-level circuit definition.
      Also: Update at Thu Oct 11 10:55:29 EDT 2012 by tim
      Also: Merge branch 'master' into work
      Also: Corrected the spice ".import" handling so that subcircuits in the imported file are correctly associated with the main circuit. However, this highlights the problem that it is not possible to read in a spice file of subcircuits independently, and attach those subcircuits to a top-level circuit.
      Also: Another correction to formatted side-by-side printout of node fragments.
      
  38. November 2, 2012 at 3:00am
      Corrected the side-by-side illegal element partition output, which failed to separately count the indexes for the two sides and would become screwed up when either side had a permutable pin.
      Also: Update at Thu Nov 1 15:08:55 EDT 2012 by tim
      Also: Merge branch 'master' into work
      Also: And one more correction for printing the circuit summary when the 2nd circuit has more elements than the first.
      
  39. November 3, 2012 at 3:00am
      Some minor changes affecting printed output: Notice of flattening unmatched instances prior to comparison moved from console to comp.out. Illegal node partition output now lists all pin names for permutable pins, so as to avoid confusion.
      Also: Update at Fri Nov 2 10:30:49 EDT 2012 by tim
      Also: Merge branch 'master' into work
      Also: Corrected the output for command "nodes" so that it doesn't break on seeing a pin, and will continue until it finds a valid node name to print.
      Also: Another addition to printout for "nodes" command, to add "(port of. . .)" when the only connection found is a port of the cell.
      Also: Corrected another error: Netgen ignores partitions with two elements, which cannot be usefully subdivided, and apparently parts of the code depend on partitions being larger than one item. However, it failed to mark partitions with two elements from the same circuit as illegal. Changed code to make a quick check at the end of an iteration for partitions with 2 items from the same circuit, and mark those partitions as illegal. This results in a complete dump of all non-matching elements and nodes.
      Also: Correction to most recent code change to create a 1-deeper nesting of lists when creating a Tcl list of node and element partitions.
      
  40. November 4, 2012 at 3:00am
      Addition of "-list" option to commands "print", "elements ", and "nodes ", and the addition of a 2nd optional argument to command "print" which can be "legal" or "illegal", to restrict printing to only legal or illegal partitions. The "-list" option passes back a Tcl list to the interpreter, instead of printing human-readable content to the console. This is the base code needed to write a GUI for the LVS function.
      Also: Update at Sat Nov 3 13:39:15 EDT 2012 by tim
      Also: Merge branch 'master' into work
      
  41. April 27, 2013 at 3:00am
      Corrections to build process thanks to the Gentoo Linux developers, especially Michael Weber.
      Also: Update at Fri Apr 26 09:31:45 EDT 2013 by tim
      Also: Merge branch 'master' into work
      
  42. May 14, 2013 at 3:00am
      Corrected the LVS script to flatten circuits that match locally but fail to resolve automorphisms. Unfortunately, visual inspection in the test case suggests that the automorphisms should have been resolved. Nevertheless, failure to resolve automorphisms should result in subcircuit flattening.
      Also: Update at Mon May 13 11:14:15 EDT 2013 by tim
      Also: Merge branch 'master' into work
      Also: Corrected a rather bad error in handling global nodes in which the code to end on the last pin of a subcircuit call was wrong, allowing the netlist to get totally screwed up while resolving global nodes used in a subcircuit.
      
  43. May 18, 2013 at 3:00am
      Added some ability to parse and handle parameters for subcircuits and subcircuit calls. Currently, parameters describing equations are not evaluated, but the parameters are at least parsed and saved, and do not interfere with the parsing of port connections and subcircuit names.
      Also: Update at Fri May 17 12:17:44 EDT 2013 by tim
      Also: Merge branch 'master' into work
      Also: Corrected an error caused by having a global node name that is not used anywhere in the top-level cell.
      
  44. May 21, 2013 at 3:00am
      Found an obscure error where a cached nodename was sought using an index higher than the number of nodes. This error may have had its roots elsewhere, but the crash condition has been eliminated.
      Also: Update at Mon May 20 19:36:01 EDT 2013 by tim
      Also: Merge branch 'master' into work
      
  45. May 23, 2013 at 3:00am
      Added some CDL-netlist syntax parsing to the SPICE netlist reader. Also, the startup script now treats anything on the command line as a Tcl statement to evaluate, so a single-line command like "lvs" can be passed to netgen directly from the command line.
      Also: Update at Wed May 22 13:16:37 EDT 2013 by tim
      Also: Merge branch 'master' into work
      Also: Implemented new command "ignore class ", to force removal of certain classes from the database. Should be used with caution. Example: remove diodes that cannot be properly extracted from the layout, or remove parasitic devices (if they are separable from "real" devices by being the only ones not using a model name).
      
  46. May 24, 2013 at 3:00am
      Added rudimentary support for parameters passed from a subcircuit to a device. Only works for a hierarchy depth of 1 at the moment.
      Also: Update at Thu May 23 16:58:37 EDT 2013 by tim
      Also: Merge branch 'master' into work
      
  47. May 25, 2013 at 3:00am
      Removed a limitation in netgen that restricts input lines to 500 characters. Now, input lines are allocated as necessary to accept input lines of arbitrary length.
      Also: Update at Fri May 24 13:35:49 EDT 2013 by tim
      Also: Merge branch 'master' into work
      
  48. May 26, 2013 at 3:00am
      Corrected an error in the allocation of an expanded memory block for line input.
      Also: Update at Sat May 25 13:24:55 EDT 2013 by tim
      Also: Merge branch 'master' into work
      
  49. May 29, 2013 at 3:00am
      Various corrections and enhancements. Changed the hierarchy stack creation so that it more precisely matches cells by name from the hierarchy bottom, and works its way back up by level. Corrected some of the handling of global nodes when promoting to ports.
      Also: Update at Tue May 28 12:00:39 EDT 2013 by tim
      Also: Merge branch 'master' into work
      
  50. May 30, 2013 at 3:00am
      Several corrections to netgen, changed the SPICE reader's behavior to avoid copying the cellname as a prefix to the instance name if the instance name already has the cellname in it. Also, fixed an error that would prevent proper LVS where dummy nodes had been added to the 2nd circuit to match unconnected pins in the 1st circuit.
      Also: Update at Wed May 29 18:03:59 EDT 2013 by tim
      Also: Merge branch 'master' into work
      
  51. May 31, 2013 at 3:00am
      Last final set of modifications to hierarchical LVS; torture test example now agrees between hierarchical and non-hierarchical netlists.
      Also: Update at Thu May 30 14:46:13 EDT 2013 by tim
      Also: Merge branch 'master' into work
      
  52. June 5, 2013 at 3:00am
      Corrected an error in which an empty hierarchy stack during SPICE read was interpreted as an error, while it may simply mean that no nodes, instances, or devices were created prior to the first subcircuit definition. The stack should always be popped on seeing ".ENDS" unless the stack pointer itself is NULL.
      Also: Update at Tue Jun 4 19:10:07 EDT 2013 by tim
      Also: Merge branch 'master' into work
      
  53. September 24, 2013 at 3:00am
      Update at Mon Sep 23 22:18:32 EDT 2013 by tim
      
  54. January 8, 2014 at 3:00am
      Corrected an error where the style of prepending "X" to an instance name caused problems where a net named, e.g., "NOR2X1_1/Y" would be confused with an instance pin named, e.g., "XNOR2X1_1/Y". This has been corrected by naming instance pins using, e.g., "/NOR2X1_1/Y", although it would probably be better to use a character like '*' that would be illegal in a SPICE netlist rather than one that is commonly used in netlisting tools and therefore likely to show up as a node name in a netlist.
      Also: Update at Tue Jan 7 12:06:25 EST 2014 by tim
      Also: Merge branch 'master' into work
      Also: Cleanup of the printout of the "elements" and "nodes" commands to prevent them from requiring or printing the leading "/" prepended to instance names.
      
  55. February 6, 2014 at 3:00am
      Experimental code implementing case-insensitive hashing and comparison. Currently the loading of a SPICE file will force case-insensitive hashing, and comparing two SPICE files will force case-insensitive comparison. There needs to be individual control over the handling of each file. Most LVS is done between SPICE format files and there may never be a need for that kind of control.
      Also: Update at Wed Feb 5 20:38:37 EST 2014 by tim
      Also: Merge branch 'master' into work
      
  56. April 11, 2014 at 3:00am
      Cleaned up fscanf() calls in netfile.c to prevent array overruns.
      Also: Update at Thu Apr 10 09:57:42 EDT 2014 by tim
      Also: Merge branch 'master' into work
      
  57. May 11, 2014 at 3:00am
      Corrected an error that causes netgen to crash on a cell with no elements. This doesn't resolve problems with running hierarchical LVS on such a cell, but at least it stops the crashing.
      Also: Update at Sat May 10 10:59:53 EDT 2014 by tim
      Also: Merge branch 'master' into work
      
  58. May 13, 2014 at 3:00am
      Several key Tcl commands like "run" and "verify" no longer generate an error code for an empty cell. This prevents LVS from prematurely quitting when encountering a subcell with no contents.
      Also: Update at Mon May 12 12:04:22 EDT 2014 by tim
      Also: Merge branch 'master' into work
      
  59. May 27, 2014 at 3:00am
      Update at Mon May 26 09:55:09 EDT 2014 by tim
      
  60. May 28, 2014 at 3:00am
      Update at Tue May 27 19:10:19 EDT 2014 by tim
      
  61. May 30, 2014 at 3:00am
      Update at Thu May 29 10:52:49 EDT 2014 by tim
      
  62. May 31, 2014 at 3:00am
      Update at Fri May 30 14:41:23 EDT 2014 by tim
      
  63. June 1, 2014 at 3:00am
      Update at Sat May 31 14:50:56 EDT 2014 by tim
      
  64. August 21, 2014 at 3:00am
      Modified netgen.tcl to avoid using the "wm" command if Tk is not loaded. That single usage prevents netgen from being called in batch mode through tclsh; otherwise, it can run without the need for an X11 display present, greatly enhancing its portability.
      Also: Update at Wed Aug 20 17:20:40 EDT 2014 by tim
      Also: Merge branch 'master' into work
      Also: Corrected an error in which netgen loses filename information about SPICE "libraries" (for example, CDL files) that have no components on the top level. Without a filename attached to the file number, netgen is no longer able to differentiate between cells belonging to that filename and other filenames. Netgen now registers an empty cell with the filename, which solves the problem.
      
  65. August 28, 2014 at 3:00am
      Attempted to resolve a number of issues where having a low-level device in one circuit with the same name as a subcircuit in the other circuit causes a crash. Did not completely resolve this issue.
      Also: Update at Wed Aug 27 14:57:24 EDT 2014 by tim
      Also: Merge branch 'master' into work
      
  66. August 30, 2014 at 3:00am
      Corrected the SPICE file read routine so that file name in a ".include" statement are interpreted relative to the path of the file that included them, if the filename contains a relative path.
      Also: Update at Fri Aug 29 14:49:15 EDT 2014 by tim
      Also: Merge branch 'master' into work
      
  67. September 5, 2014 at 3:00am
      Added some missing model types to the "model" command. Also: Removed Tk calls from netgenexec.c, so that the executable "netgenexec" or the script call "netgen -noconsole" will run without requiring graphics accessibility.
      Also: Update at Thu Sep 4 09:57:44 EDT 2014 by tim
      Also: Merge branch 'master' into work
      Also: Implemented new command option "permute forget".
      
  68. September 6, 2014 at 3:00am
      Corrected an error introduced into recent code that prevents the use of "equate classes" in the setup file, as it would refuse to work until a netlist was read in. Only the "equate nodes" and "equate elements" need to have a netlist in memory to run; "equate classes" does not.
      Also: Update at Fri Sep 5 10:04:53 EDT 2014 by tim
      Also: Merge branch 'master' into work
      Also: Quick correction: "equate pins" also requires that a netlist have been read in first. Only "equate classes" can be run prior to a netlist read.
      Also: Corrected a very bad error in which an "include" statement in a SPICE file would re-read the parent file instead.
      Also: Rather a lot of coding, fixed a lot of memory allocation issues which get the tool a longer way toward being able to implement a reinitialization without crashing, and fixes problems where recent changes caused previously working LVS runs to break. Appears to be back to normal now.
      
  69. September 8, 2014 at 3:00am
      Corrected a major problem with subcircuit using multiplier "M=", which was generating unconnected instances for all but the first device.
      Also: Update at Sun Sep 7 16:11:44 EDT 2014 by tim
      Also: Merge branch 'master' into work
      
  70. September 9, 2014 at 3:00am
      Updated a few portions of the configure script to resolve differences with the similar configure script used for magic-8.0.
      Also: Update at Mon Sep 8 08:47:31 EDT 2014 by tim
      Also: Merge branch 'master' into work
      
  71. September 13, 2014 at 3:00am
      Sweeping changes to the code to stop the silliness with prepended underscores, and let cellnames be cellnames, and track which file is which throughout the comparison process.
      Also: Update at Fri Sep 12 14:54:31 EDT 2014 by tim
      Also: Merge branch 'master' into work
      
  72. September 14, 2014 at 3:00am
      Changed the "readnet" command so that it just returns the file number of a file if it has already been read, instead of attempting to read it again.
      Also: Update at Sat Sep 13 21:06:28 EDT 2014 by tim
      Also: Merge branch 'master' into work
      
  73. September 15, 2014 at 3:00am
      Reworked the "equate classes" command so that it now works correctly with the latest code. Note, however, that the command needs an additional option where one can specify both the cellname and the file.
      Also: Update at Sun Sep 14 11:47:43 EDT 2014 by tim
      Also: Merge branch 'master' into work
      
  74. September 16, 2014 at 3:00am
      Minor correction of the use of strchr() when it should have been strrchr() when searching for the '.' before a file extension.
      Also: Update at Mon Sep 15 08:12:34 EDT 2014 by tim
      Also: Merge branch 'master' into work
      

Revision information on Netgen 1.3:

Netgen revision history: Version 1.3

0. November 15, 2004
   Changed the "make" method to GNU autoconf. Revised the directory structure to put most of the Tcl-based stuff into the "tcltk" subdirectory. The source itself is essentially unchanged from version 1.2. Confirmed compile and run for both the Tcl and non-Tcl versions.
1. August 6, 2005
   Updated parts of the "make" process to match additions to magic and xcircuit, and to address issues related to compile and install on Cygwin. Cygwin users should read the compile and install instructions on magic for Windows.
2. September 3, 2005
   Added Xilinx support. Thanks to Peter Welch for providing the patch files. Thanks to Ingo Cyliax for the code itself, which was added to a branch of netgen at the University of Indiana, and about which I was unaware until Peter brought it to my attention. Apparently that code branch is no longer available for download from the CS department at Indiana.
   
   Also: Changed the Makefile process to parse the file VERSION for version and revision information, not the directory name. Switched the directory to the name with the version number ("netgen-1.3.2") and the symbolic link to the package name ("netgen"). It was gently pointed out to me that I had this ass-backwards.
3. September 6, 2005
   Added support for reading bipolar transistors from SPICE decks.
4. September 7, 2005
   Made some changes to prevent crashing on unexpected input (in particular, undefined subcircuits) in SPICE decks. Also, added the command "readlib" for reading Actel and Xilinx libraries (formerly required use of "readnet actel|xilinx" plus an unused dummy argument, due to an error in the Tcl command-line processing). A warning is posted if an attempt is made to write a Xilinx or Actel format file without first reading the associated library.
5. Februrary 23, 2006
   Distribution compliance changes: CAD_HOME redefined to be the same as "libdir", so that "libdir" can be defined independently of "prefix" when running configure without screwing up everything.
6. Februrary 24, 2006
   Changed CAD_HOME to CAD_ROOT to avoid breaking backwards compatibility.
   Also: Added DESTDIR to all the Makefile install procedures to support "sandbox" compilation and installation.
7. June 14, 2006 at 2:40am
   Initial revision
   Also: source distribution
   Also: Added distclean target and dist target Added RPM spec file
   Also: Removed extra configure logs
8. November 22, 2007 at 2:40am
   Added handling for device types "z", "r", "c", and "b" when using the netgen command "writenet sim". However, device properties (length, width, resistance, etc.) are still not handled. . .
9. November 23, 2007 at 2:40am
   Added rudimentary support for device properties. For the moment, apart from the important aspect of having a database representation for device properties such as length, width, resistance, and capacitance, there is support for reading device properties from SPICE files and writing those that are supported by the sim format to .sim files. It is my intention to eventually support property comparisons in LVS.
10. December 1, 2007 at 2:40am
    Corrected some errors where strdup() and free() were called instead of their Tcl counterparts.
11. April 27, 2013 at 3:00am
    Corrections to build process thanks to the Gentoo Linux developers, especially Michael Weber.
    
12. September 24, 2013 at 3:00am
    Update at Mon Sep 23 22:18:32 EDT 2013 by tim
    
13. April 11, 2014 at 3:00am
    Cleaned up fscanf() calls in netfile.c to prevent array overruns.
    Also: Update at Thu Apr 10 09:57:33 EDT 2014 by tim
    Also: Merge branch 'master' into work
    
14. May 27, 2014 at 3:00am
    Update at Mon May 26 09:55:09 EDT 2014 by tim
    
15. May 28, 2014 at 3:00am
    Update at Tue May 27 19:10:18 EDT 2014 by tim
    
16. May 30, 2014 at 3:00am
    Update at Thu May 29 10:52:49 EDT 2014 by tim
    
17. May 31, 2014 at 3:00am
    Update at Fri May 30 14:41:23 EDT 2014 by tim
    
18. June 1, 2014 at 3:00am
    Update at Sat May 31 14:50:55 EDT 2014 by tim
    

Revision information on Netgen 1.2:

Netgen revision history: Version 1.2

0. March 12, 2003
   Fixes the the "make config" process for Tcl/Tk compile. Also, finished implementing the Tcl "log" command for log file output, and added the script-level "lvs" command to replace the original standalone program "netcomp".
1. March 24, 2003
   Corrections to TCL command interface.
2. March 26, 2003
   This version was never officially released.
3. March 31, 2003
   Changes for interoperability with magic and IRSIM.
4. April 3, 2003
   Changes to save position information in element names for transistors read from .sim files.
5. September 22, 2003
   Added the capability to handle "M=" syntax in SPICE files for declaring multiple transistors with equal size and connections.
6. September 30, 2003
   Fixed an unfortunate problem with the "lvs" script command in which it implies that circuits which pass the low-level connectivity comparison match correctly. In fact, these circuits may have errors. The fix checks this condition, performs the high-level resolution of automorphisms, and reports a final pass/fail condition.

Revision information on Netgen 1.1:

Netgen revision history: Version 1.1

0. December 14, 2002
   This is a first draft. Only a few things have been changed in this release other than the Tcl/Tk port. There is now support for capacitors, resistors, bipolars, poly-poly capacitors and resistors built with the pseudo-poly layer in magic, in the SPICE, sim, and ext format read routines. The Tcl version has a completely revamped command set, better matching the general practices of Tcl command syntax (mainly meaning commands are full words rather than single letters). In addition, the command sets for "netgen" and "netcmp" have been combined.
1. January 13, 2003
   Massive speedup of several critical and badly-written functions; reduced from O(N^2) to O(N). The "compare" command is now virtually instantaneous. Commands "nodes" and "elements" now give more relevant information regarding specific points in the network. "sim" format retains position in the element names (for FET and FET-like elements) for convenient traceback to a layout or schematic.

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Last updated: April 4, 2024 at 2:00am