Netgen 1.5

Table of Contents

Using Netgen Version 1.5
Integrating Netgen With Tcl/Tk-Based Magic

Using Netgen version 1.5:

Command-line invocation:

netgen [-noconsole] [command_line]
netgen -batch command_line
With no arguments, netgen will bring up a Tk console window with an interpreter prompt, waiting for command input from the user (see command set, below).

With argument -noconsole, there will be no console window, and the interpreter prompt will be in the terminal.

For Netgen version 1.4 and eariler, the command_line argument is unavailable. With netgen version 1.5 and later, any valid netgen (or Tcl/Tk) command may be passed through command_line and operates as a type of batch-mode processing; for example,

netgen lvs circuit1.spc circuit2.spc
For batch-mode processing of multiple commands, put the commands into a file and source that file through the command line; for example,
netgen source batch_script.tcl
Note that a batch script will end by returning to the Tcl interpreter unless it ends with a "quit" command, or if the command-line argument -batch is passed to netgen. The -batch command implies "noconsole" mode, and exits after executing the command_line argument. If no command_line is present, then netgen prints version information and exits.

Versions of Netgen compiled without Tcl will not have a console window and will simply generate a prompt at the terminal, and will accept a limited set of single-character commands. Because the Tcl-based version is vastly superior, usage information on this website will primarily focus on that version.

Using Tcl-based Netgen:

The Tcl command-line commands completely replace the original command-line interface, which consisted on one-key entries in a hierarchically stacked format, difficult to use. I have removed the interface and replaced it with Tcl command-line commands plus a few scripts. These are outlined below. The original X11 interface was a complete and unnecessary disaster and has been removed. With the Tcl interface, it could presumably be rewritten in Tk, although personally, I can't see why anybody would want to.

The most common use of "netgen" is to make use of its network comparison feature to compare a layout generated from magic with "extract" and "ext2spice" commands against a layout generated from a schematic (e.g., xcircuit). Starting with version 1.2, there is a script-level command which performs the sequence of commands above. This command is:

Arguments circuit1 and circuit2 are both filename and cellname, and assume that each file contains a top-level cell that is not defined as a subcircuit (thus the filename becomes the name of the top-level cell). The alternative syntax is to give, for one or both of the circuits, a separate file and cell name. This covers cases where the file does not contain a top-level cell, and also cases in which one wants to run LVS starting at a level of hierarchy lower than the top. logfile is the file to dump all output, and defaults to "comp.out" if not specified. Note that certain useful information, such as the initial report on the two files, and the final "yea or nay" result, is duplicated both to the log file and to the console (or terminal) window. The output file should be consulted for all detailed information about netlist errors. The optional file setup_file is a Tcl-format file containing any commands that should be run after both files are read in but before the comparison is made. Typically, this will contain information on how to map device model names or subcircuit names between the two files, and how to permute pins on subcircuits.

The most common use of setup_file is to map subcircuit names between the two circuits. Each line of the file should contain the command

equate classes name1 name2
declaring that device class or subcircuit name name1 in circuit1 is equivalent to device class or subcircuit name name2 in circuit2. If the setup_file is not present, then the default setup file name "setup.tcl" will be read, if it exists. If not, then every device class in circuit1 must have the same name as that used in circuit2, or else the circuits will never match. In SPICE files, each semiconductor device has a model name, which netgen uses as the device class. Devices with different models are compared independently. In addition, if no setup file is specified, then default permutations are allowed (transistor sources and drains permute, and resistor endpoints permute).

The command sequence used by the lvs command to compare two netlists is as follows:

Arguments circuit1 and circuit2 are filenames. They do not need to have the file extension if a standard extention (.sim, .spc, .spice) is used, but do need to contain any directory path components (relative to the current working directory).

For circuits which do not match, it will be necessary to run the command "verify" to look at the list of illegal elements and nodes.

Note that the "verify" command produces copious output. Generally, it is preferable to use the "log" command to dump this output to a file. The command "verify only" produces just one line stating whether or not the circuits match. The output can be terminated at any time with a Control-C interrupt into either the terminal or console windows.

Using the non-Tcl-based (legacy) Netgen:

Information on the legacy version of netgen can be found in the source doc directory, in the file netgen.doc. This text file has been formatted for a web browser and can be found here.

Standalone programs

For a long time, I did LVS by compiling netgen and using the standalone program "netcomp" for the LVS part, ignoring the rest of the "netgen" package, which largely deals with handling the loading and conversion of different netlist formats.

Version 1.3 dispenses with the standalone programs, instead making the command-line interface more accessible. See the description of Tcl commands below for details.

Tcl Command-Line Interface (for Netgen 1.5 and above)

Common options: Netgen 1.5 has a more consistent command set with common options for indicating cell names. Previous versions of netgen would not differentiate between files when searching for cells, so cells with the same could be confused between files when the cell was queried from the command line. When two cells were compared, one would have an underscore prepended to all the cell names so that they could be differentiated from cells in the other file. However, that was an arbitrary solution, and as it did not address the issue of how to tell apart cells of the same name in different files from the command line. Netgen 1.5 (from revisision 9) takes a different approach of having a consistent interface in which cells must always be uniquely identified. The readnet command returns a number (not the operating system's file number) that can be used to identify the file and all of its cells in subsequent commands. However, there are several ways that a cell can be identified from the command line, as long as the method ensures that the cell name is unique. Any of the following ways will work:
cellname
The cellname alone identifies the cell if there are no other cells of the same name belonging to other files.
{cellname file_number}
The file_number is the value returned from the readnet command that loaded the file containing cellname. When a cell is identified by a pair of values like this, they must be presented to the Tcl interpreter as a list, which means that they must be enclosed in braces (double-quotes will also work).
{file_number cellname}
In a two-item list, cellname and file_number may be in either order.
{filename cellname}
The filename is the name of the file containing the cell cellname. When applied as an argument to the lvs command, this form is required if the file filename has not yet been read; the filename alone (see below) is acceptable if cellname is the top-level cell (that is, it is the same as filename).
{cellname filename}
In a two-item list, cellname and filename may be in either order, unless used as an argument to the lvs command when filename has not yet been read in (see above).
filename
If a file contains a top-level cell that is not in a subcircuit, then that top-level cell has no internal name, and netgen gives the cell the same name as the file (including the extension). So the filename is equivalent to the top-level cell in this case.
file_number
Like the syntax above, a single number can refer to the top-level cell of the file that has been assigned the number file_number.
-circuit1
Refers to the first of the two circuits passed to the "lvs" procedure, or more specifically, to the "compare assign" command. This implies that the "compare assign" command must be run prior to using this method, and likewise, that the "compare assign" command itself cannot use this method.
-circuit2
Refers to the second of the two circuits passed to the "lvs" procedure, or more specifically, to the "compare assign" command. This implies that the "compare assign" command must be run prior to using this method, and likewise, that the "compare assign" command itself cannot use this method.
In the list below, the term valid_cellname is used to refer to any of the syntax methods above for describing a unique cell name.

The two-item list form was introduced with netgen version 1.4.13 but was not extended to include all forms, or extended for use in all commands requiring a cell name, until version 1.5.9.

Netlist manipulation commands:

canonical valid_cellname
Return a 2-item list containing the cell name and the file number of the cell indicated by valid_cellname. See the description above for the syntax of valid_cellname.
readnet [format] filename [filenum]
read a netlist file (default format=auto). Auto-detection first looks for files with standard extensions. If no file is found with a standard extention, then the file is checked for the initial character, which is always "*" in SPICE files and "|" in .sim files.

Returns the file number for the file, which can be used in other commands to reference the file and its cell hierarchy.

If filenum is specified, then the contents of the cell are added to the netlist of file number filenum. This option may be used if subcells are in separate files without the use of ".include" statements. However, for reading models, standard cells, or subcircuits as "black boxes", use readlib instead (see below). The option may also be used to assign file numbers to netlists manually.
readlib format [filenum]
Initialize a library module definition, where format is one of actel, spice, or xilinx. The library definitions need to be initialized prior to reading any netlist file that is to be rewritten as "writenet actel filename", "writenet xilinx filename", or as a SPICE netlist with the definitions from the library included in the file.

Returns the file number for the file, which can be used in other commands to reference the file and its cell hierarchy.

In general, a library is not useful as a standalone file, and normally filenum will be passed to the command to attach the library to a specific netlist. If the library contents are common to more than one netlist, then the readlib command should be issued once for each netlist.
writenet format filename
write a netlist file
flatten valid_cellname
flatten a hierarchical cell.

Note: Always flatten a cell in a hierarchical format (such as SPICE) before writing a flat format, even if the original netlist is already flat. Otherwise, the flattened namespace will not be cached, and the write process will incur a horrific performance hit.
flatten class [cellname] valid_cellname
In this form of the flatten command, the whole cell database is searched for instances of the cell valid_cellname, which are then flattened by merging them into the parent cell. From netgen version 1.5.53, the optional cellname allows instances of the cell valid_cellname to be flattened only within the specified parent cell. Note that "cellname" is not in the general form of "valid_cellname", but is the cell name only. The cell is assumed to be in the same circuit as valid_cellname.
model valid_cellname [model]
model blackbox on|off
declare a cell to be specific model type. Normally, model types are derived from low-level device calls in an input file (such as SPICE). This command will override the assigned model type, assuming that the cell has the correct number of pins for the model type. The supported low-level device model types are: nmos (3 or 4 port), pmos (3 or 4 port), pnp, npn, resistor, capacitor, diode, inductor, or xline. A low-level device can be treated as a subcircuit by declaring model to be subcircuit. A circuit declared to be model blackbox will only recognize the pin names and pin order but will otherwise ignore the subcell contents.

Without option model, return the device model of the cell valid_cellname.

With specific option model blackbox, any subcircuit read in that has no contents will be treated as a "black box" (essentially treated like a device) if this option is on. If off, the subcircuit will treated as an actual subcircuit with no contents.
nodes [[-list] element] valid_cellname
print nodes of an element or cell
with option -list, return a list of nodes to the Tcl interpreter.
elements [[-list] node] valid_cellname
print elements of a node or cell
with option -list, return a list of elements to the Tcl interpreter. Element names are returned in the format "element_name/pin_name".
debug on|off|command [options...]
turn debugging on or off or debug a command. When debugging is on, the output of LVS comparisons reverts to the original, list-oriented format instead of the newer side-by-side format.
protochip
embed protochip structure
instances valid_cellname
list instances of the cell
contents valid_cellname
list contents of the cell
describe valid_cellname
describe the cell
cells [list] [-all] [-top] [valid_filename]
print known cells
option -all: print all cells, including primitives. If valid_filename is given, then restrict the listing of cells to those belonging to the specified file.

option -top: print the top-level cells. There is one top-level cell associated with each loaded file. If the loaded file is a library, the top-level cell may be empty.

Note: valid_filename takes the form of syntax for valid_cellname; however, a cell name that is not a top-level cell will act as if the filename of the file containing that cell has been passed to the command.
ports valid_cellname
print ports of the cell
leaves [valid_cellname]
print leaves of the cell
quit
exit netgen and Tcl
reinitialize
reintialize netgen data structures
log [file name|start|end| reset|suspend|resume|echo]
enable or disable output log to file named file.
help
print basic usage information
Netlist comparison commands:
compare valid_cellname1 valid_cellname2
declare two cells for netlist comparison. Subcircuits that are not declared equivalent or that do not have the same name in both cells are flattened. Otherwise, subcircuit instances will be compared as black-box devices, without comparison of their contents (if any).
compare hierarchical [valid_cellname1 valid_cellname2]
do a full hierarchical comparison. The first call must declare the two top-level cells valid_cellname1 and valid_cellname2. The cell hierarchy will be searched; all cells with matching names or cells that are declared equivalent will be saved in a stack. All cells whose match in the other top-level cell's hierarchy cannot be determined will be flattened. Upon the completion of the search, the top of the stack (the bottommost cells in the hierarchy) will be prepared for comparison. Subsequent calls to compare hierarchical should be called without any arguments. Each time compare hierarchical is called, the next pair of cells is taken off of the top of the stack and prepared for comparison. Once there are no cell pairs left to compare, compare hierarchical returns the string "empty queue".
compare assign [valid_cellname1 valid_cellname2]
Assign netlists to be compared, but take no further action. This allows all future commands requiring valid_cellname to use the generic names "-circuit1" and "-circuit2" to refer to the two netlists, respectively.
iterate
do one netlist comparison iteration
summary [elements|nodes]
summarize internal data structures
print [-list] [elements|nodes|queue] [legal|illegal]
print full report on the internal data structures. This is a list of the partitions generated by the comparison algorithm.
with option elements, print only the element partitions.
with option nodes, print only the node partitions.
with option queue, print the comparison queue.
with option legal, print only legal (matching) partitions.
with option illegal, print only illegal (non-matching) partitions.
with option -list, return a nested list with the information, where each item in the list is one partition, and each item is a list of two parts, one for each circuit, and each part is a list of either element pins, or nodes. The -list option may only be used with either print elements or print nodes.
run [converge|resolve]
with option converge: run netlist comparison to completion (convergence)
with option resolve: run to completion and resolve automorphisms
verify [elements|nodes|only| equivalent|unique]
verify results
automorphisms
print automorphisms
equate [elements|nodes|classes] name1 name2
equate pins
with option elements: equate two elements
with option nodes: equate two nodes
with option classes: equate two device classes.
The name name1 must belong to the first of the two circuits being compared and name2 must belong to the other one.
with option pins: equate pins in the two cells being evaluated. This requires that two cells have been declared with the compare hierarchical command, and that LVS has run to convergence on any pair of cells in the stack (see compare hierarchical), and the netlists verified as matching. The equate pins command will sort the ports of one cell to match those of the other.
ignore class valid_cellname
Remove all instances of the device class "valid_cellname" from the database, and prevent any subsequent addition of any instance of the class when reading a netlist file. Use with caution! Can be useful in some cases, such as to ignore diode devices that cannot be recognized during layout extraction, or to ignore all parasitic devices in a netlist file. Available on Netgen versions 1.4.45 and higher.
global valid_cellname netname [...]
This command makes the net named netname in the hierarchy of cell valid_cellname into a global node. The cell valid_cellname must exist in the database (it must have already been read into netgen). This command is typically used within the setup file to assert which nodes in a file need to be declared global. For instance, if the SPICE netlist "file.spice" contains a subcircuit using the default SPICE ground node name "0", then the setup file would need the line "global file.spice 0". Note that a SPICE netlist file can contain a forward reference to a global node name using the ".global name" card, in which case the global statement is not needed.
convert valid_cellname
This command searches cell valid_cellname for global nodes, and converts each one into a local node while adding that node to the pin list of the cell. The database is searched for all instances of valid_cellname, and the global node is passed from the parent cell to the instance by way of this pin.
permute [transistors|resistors|capacitors]
permute [pins] valid_cellname pin1 pin2
permute forget valid_cellname pin1 pin2
with option pins: permute pins pin1 and pin2 on device valid_cellname. If more than two pins may be permuted, this command may be issued multiple times between pairs of pins.
With option forget: remove any permutation between pins pin1 and pin2 on device valid_cellname. This option is provided for situations where it is more convenient to first apply the default permutations and then specify the exceptions individually (netgen 1.4.67 and later only).
With option transistors: enable transistor source/drain permutations for any device recognized as a MOSFET.
With option resistors: enable permutations of resistor endpoints.
With option capacitors: enable permutations of capacitor top and bottom plates. Because capacitor top and bottom plates have different parasitics, capacitor plate permutation is not normally enabled.
With no options: enable transistor source/drain and resistor endpoint permutations.
property valid_cellname|device_name
property valid_cellname|device_name add { key type tolerance } ...
property valid_cellname|device_name remove [key ... ]
property valid_cellname|device_name tolerance { key tolerance } ...
property valid_cellname|device_name merge { key merge_type } ...
property valid_cellname|device_name serial|parallel enable|disable ...
property parallel none|all
with no options other than a valid cellname, return a list of triplets, each triplet being a list of three items representing a property of the cell. Items are, in order, the name (key) of the property, the type of property (which is one of string, integer, double, value, or expression), and the tolerance for checking (which is type-dependent). Note that properties of cells, as opposed to instances of cells, do not have values. The main purpose of the property command is to establish which device properties will be compared, and what will be the criterion for comparison. When no tolerance value is given, then the default tolerances of 0, for integer values, and 0.01 (1 percent) for floating-point values, will be assigned.
With option add, the full property description may be given as a triplet, or tolerance may be omitted, in which case the default tolerance will be used; type may be omitted, in which case the type will be either string or double, depending on the tolerance. Generally, the full description is preferred to avoid ambiguity.
With option remove, if no other option is given, the all properties will be removed from the device or cell.
With option merge, the behavior of devices combining in parallel or in series may be declared. The key is a valid property name for the device, while merge_type may be one of add, add_critical, par, or par_critical. add and add_critical indicate that when two devices combine in parallel, the values of the devices for the indicated parameter will be summed. par and par_critical indicate that the values will be parallel-combined (1/((1/A)+(1/B))). If the devices combine in series (see below), the two methods are swapped (summing for par and parallel combination for add). The "_critical" indicates that the comparison will actively attempt to merge devices by combining this parameter to make a better match. Without "_critical", the parameters are combined whenever the critical parameters are combined, but will not be used to actively resolve differences between the two circuits.
With option serial or parallel, the device is declared to be able to be combined in parallel or in series, depending on the additional argument enable or disable. By default, all devices are allowed to be combined in parallel, while only resistors and inductors are allowed to be combined in series. This command can be used to override the defaults. Note that this option does not determine how the devices will be combined, for which the merge option is needed (see above). This option lets series or parallel devices be treated as a single unit, such that any differences between the series/parallel networks of the circuits being compared will be treated as property errors, not topological (wiring) errors. Also note that devices connected in series must connect on the first two pins, and any additional pins must be connected to the same nodes on all devices.
Option property parallel none removes the default parallel merging behavior from every device. Note that parallel merging is enabled for all devices and subcircuits by default, so this is the only way to change the underlying behavior. Subsequent calls to the property command can be used to reinstate the parallel merging behavior on a per-device basis.
exhaustive
toggle exhaustive subdivision
restart
start over (reset data structures)
matching [element|node] name1
return the corresponding node or element name in the compared cell
Scripted Tcl procedures:
lvs valid_cellname1 valid_cellname2 [setup_file] [logfile]
Run the netlist comparison commands to load and compare the two netlists, leaving the bulk of the output in the file logfile (defaults to "comp.out" if unspecified), with a succinct summary printed to the terminal. If the optional setup_file is present, source this file prior to comparing the circuits. This file is Tcl-syntax compatible, and normally contains netgen commands that affect the way LVS is run. Typical commands used in the setup file are "equate classes..." and "permute...". If setup_file is not present, netgen will check for the default setup filename "setup.tcl", and source it if it exists. If no setup file exists, then default permutations (transistor source/drain and resistor endpoints) are used, and no assumptions are made about class equivalences. The LVS comparison is hierarchical (see command "compare hierarchical", above). If the files to be compared have a top-level structure (that is, components that are not inside a subcircuit definition), then the top-level cell takes the (full) name of the filename (see the description of "valid_cellname" syntax at the top of the command list). If the files contain all subcircuit definitions, or one wishes to compare cells below the top level of hierarchy, or the files have not been read prior to calling the lvs procedure, then the two-item list form {filename cellname} for valid_cellname must be used.

Tcl Command-Line Interface (for Netgen 1.4 and below)

Note that the command-line interface for version 1.4 does not include the general form for specifying cells shown above for version 1.5. Be wary of cell names that can be confused between two different files.

Netlist manipulation commands:

readnet [format] file
read a netlist file (default format=auto). Auto-detection first looks for files with standard extensions. If no file is found with a standard extention, then the file is checked for the initial character, which is always "*" in SPICE files and "|" in .sim files.
readlib format
Initialize a library module definition, where format is either actel or xilinx. The library definitions need to be initialized prior to reading any netlist file that is to be rewritten as "writenet actel filename" or "writenet xilinx filename".
writenet format file
write a netlist file
flatten cell
flatten a hierarchical cell. Note: Always flatten a cell in a hierarchical format (such as SPICE) before writing a flat format, even if the original netlist is already flat. Otherwise, the flattened namespace will not be cached, and the write process will incur a horrific performance hit.
flatten class cell
In this form of the flatten command, the whole cell database is searched for instances of the cell cell, which are then flattened by merging them into the parent cell.
model cell model
declare a cell to be specific model type. Normally, model types are derived from low-level device calls in an input file (such as SPICE). This command will override the assigned model type, assuming that the cell has the correct number of pins for the model type. The supported low-level device model types are: nmos (3 or 4 port), pmos (3 or 4 port), pnp, npn, resistor, capacitor, diode, inductor, or xline. A low-level device can be treated as a subcircuit by declaring model to be subcircuit.
nodes [[-list] element] cell
print nodes of an element or cell
with option -list, return a list of nodes to the Tcl interpreter.
elements [[-list] node] cell
print elements of a node or cell
with option -list, return a list of elements to the Tcl interpreter. Element names are returned in the format "element_name/pin_name".
debug on|off|command [options...]
turn debugging on or off or debug a command. When debugging is on, the output of LVS comparisons reverts to the original, list-oriented format instead of the newer side-by-side format.
protochip
embed protochip structure
instances cell
list instances of the cell
contents cell
list contents of the cell
describe cell
describe the cell
cells [list|all]
print known cells
option all: print all cells, including primitives
ports cell
print ports of the cell
leaves [cell]
print leaves of the cell
quit
exit netgen and Tcl
reinitialize
reintialize netgen data structures
log [file name|start|end| reset|suspend|resume|echo]
enable or disable output log to file named file.
help
print basic usage information
Netlist comparison commands:
compare cell1 cell2
declare two cells for netlist comparison. Subcircuits that are not declared equivalent or that do not have the same name in both cells are flattened. Otherwise, subcircuit instances will be compared as black-box devices, without comparison of their contents (if any).
compare hierarchical [cell1 cell2]
do a full hierarchical comparison. The first call must declare the two top-level cells cell1 and cell2. The cell hierarchy will be searched; all cells with matching names or cells that are declared equivalent will be saved in a stack. All cells whose match in the other top-level cell's hierarchy cannot be determined will be flattened. Upon the completion of the search, the top of the stack (the bottommost cells in the hierarchy) will be prepared for comparison. Subsequent calls to compare hierarchical should be called without any arguments. Each time compare hierarchical is called, the next pair of cells is taken off of the top of the stack and prepared for comparison. Once there are no cell pairs left to compare, compare hierarchical returns the string "empty queue".
iterate
do one netlist comparison iteration
summary [elements|nodes]
summarize internal data structures
print [-list] [elements|nodes|queue] [legal|illegal]
print full report on the internal data structures. This is a list of the partitions generated by the comparison algorithm.
with option elements, print only the element partitions.
with option nodes, print only the node partitions.
with option queue, print the comparison queue.
with option legal, print only legal (matching) partitions.
with option illegal, print only illegal (non-matching) partitions.
with option -list, return a nested list with the information, where each item in the list is one partition, and each item is a list of two parts, one for each circuit, and each part is a list of either element pins, or nodes. The -list option may only be used with either print elements or print nodes.
run [converge|resolve]
with option converge: run netlist comparison to completion (convergence)
with option resolve: run to completion and resolve automorphisms
verify [elements|nodes|only| equivalent|unique]
verify results
automorphisms
print automorphisms
equate [elements|nodes|classes] name1 name2
equate pins
with option elements: equate two elements
with option nodes: equate two nodes
with option classes: equate two device classes.
The name name1 must belong to the first of the two circuits being compared and name2 must belong to the other one.
with option pins: equate pins in the two cells being evaluated. This requires that two cells have been declared with the compare hierarchical command, and that LVS has run to convergence on any pair of cells in the stack (see compare hierarchical), and the netlists verified as matching. The equate pins command will sort the ports of one cell to match those of the other.
ignore class name
Remove all instances of the device class "name" from the database, and prevent any subsequent addition of any instance of the class when reading a netlist file. Use with caution! Can be useful in some cases, such as to ignore diode devices that cannot be recognized during layout extraction, or to ignore all parasitic devices in a netlist file. Available on Netgen versions 1.4.45 and higher.
global cellname netname
This command makes the net named netname in the hierarchy of cell cellname into a global node. The cell cellname must exist in the database (it must have already been read into netgen). This command is typically used within the setup file to assert which nodes in a file need to be declared global. For instance, if the SPICE netlist "file.spice" contains a subcircuit using the default SPICE ground node name "0", then the setup file would need the line "global file.spice 0". Note that a SPICE netlist file can contain a forward reference to a global node name using the ".global name" card, in which case the global statement is not needed.
convert cellname
This command searches cell cellname for global nodes, and converts each one into a local node while adding that node to the pin list of the cell. The database is searched for all instances of cellname, and the global node is passed from the parent cell to the instance by way of this pin.
permute [transistors|resistors|capacitors]
permute [pins] model pin1 pin2
permute forget model pin1 pin2
with option pins: permute pins pin1 and pin2 on device model. If more than two pins may be permuted, this command may be issued multiple times between pairs of pins.
With option forget: remove any permutation between pins pin1 and pin2 on device model. This option is provided for situations where it is more convenient to first apply the default permutations and then specify the exceptions individually (netgen 1.4.67 and later only).
With option transistors: enable transistor source/drain permutations for any device recognized as a MOSFET.
With option resistors: enable permutations of resistor endpoints.
With option capacitors: enable permutations of capacitor top and bottom plates. Because capacitor top and bottom plates have different parasitics, capacitor plate permutation is not normally enabled.
With no options: enable transistor source/drain and resistor endpoint permutations.
exhaustive
toggle exhaustive subdivision
restart
start over (reset data structures)
matching [element|node] name1
return the corresponding node or element name in the compared cell
Scripted Tcl procedures:
lvs circuit1 circuit2 [setup_file] [logfile]
lvs { file1 cell1} { file2 cell2} [setup_file] [logfile]
Run the netlist comparison commands to load and compare the two netlists, leaving the bulk of the output in the file logfile (defaults to "comp.out" if unspecified), with a succinct summary printed to the terminal. If the optional setup_file is present, source this file prior to comparing the circuits. This file is Tcl-syntax compatible, and normally contains netgen commands that affect the way LVS is run. Typical commands used in the setup file are "equate classes..." and "permute...". If setup_file is not present, netgen will check for the default setup filename "setup.tcl", and source it if it exists. If no setup file exists, then default permutations (transistor source/drain and resistor endpoints) are used, and no assumptions are made about class equivalences. The LVS comparison is hierarchical (see command "compare hierarchical", above). If the files to be compared have a top-level structure (that is, components that are not inside a subcircuit definition), then the first syntax is used, and the top-level cell takes the (full) name of the filename. If the files contain all subcircuit definitions, or one wishes to compare cells below the top level of hierarchy, then the second form may be used, where one or both circuits may be split into a list of two items, the first being the filename, and the second being the name of the subcircuit to compare. The second form was introduced with netgen version 1.4.13.

Integrating Netgen With Tcl/Tk-Based Magic

Currently, there are no specific advantages to using netgen directly under magic. It is still necessary to run the "extract" and "ext2spice" commands to generate a netlist, then run netgen's "lvs" command to compare the layout-derived netlist to a schematic-derived netlist.

Magic versions 7.5 and 8.0, as of December 2010, have an option "ext2spice hierarchical on", that will produce hierarchical netlists for LVS using the netgen "lvs" command. Of course, it is still possible to compare flattened netlists, but hierarchical comparison is vital for any large project.

See the "To-Do" section in the release notes for more on planned integration capabilities.

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Last updated: June 19, 2017 at 10:21pm