Table of Contents

Revision information on Open_PDKs 1.0

Revision information on Open_PDKs 1.0:

Open_PDKs revision history: Version 1.0

• posted: January 15, 2021 at 3:00am     version: 1.0     revision: 107
  Corrected the fill generation script to avoid dropping fill outside the chip area if the chip area is not an exact multiple of the check step. Also added a density check script for running on final GDS with fill (the output of the fill generation script).
  add GDS_FILES pointer and a KLAYOUT_TECH, PROPERTIES pointers
  Also: add @laurentc2 klayout setup to replace the current klayout setup
  Also: Update config.tcl
  Also: Updated VERSION to go along with pull request #90 from Amr Gouhar.
  
• posted: January 13, 2021 at 3:00am     version: 1.0     revision: 106
  Corrected the metal5 fill patterning, as the size of the fill shapes was changed but the associated shrink/grow rule was not adjusted along with it.
  
• posted: January 12, 2021 at 3:00am     version: 1.0     revision: 105
  Corrected an error in the magic techfile which was left over from an early implementation of MiM caps and will erase the metal layers from a MiM cap on GDS read. Also: Corrected the netlists for the I/O power and ground cells to work around an error with the OGC* pins, which are internally connected. Modified the netgen setup file to allow the number of columns to be adjusted through use of an external environment variable NETGEN_COLUMNS.
  Removed a wayward line from the tech file that was a non-syntactical marker and should not have been committed.
  Also: Tweaked the fill pattern slots operators to ensure a maximum fill density on a clear area that is less than the specified DRC maximum. For M5, increased the fill shape size to exceed the specified DRC minimum---this rule may need further tweaking.
  Also: Added a cifoutput section called "density" for more efficient density checking.
  
• posted: January 9, 2021 at 3:00am     version: 1.0     revision: 104
  Corrected the sky130_ef_io__vdda_hvc_clamped_pad cell, which had the clamp overlay cell flipped left-to-right, which swaps the proper connections to the clamp.
  Created the wrong filename for the GDS of the custom sky130_ef_io in the last commit. Also for this commit: The equivalent VSSA pad to the one corrected in the last commit also needed to be modified.
  
• posted: January 7, 2021 at 3:01am     version: 1.0     revision: 103
  Modified the magic techfile to remove the CELLRING templayer from the GDS output, as it is being replaced by the "mask-hints" method. Added mask hints to the top_gpiov2 cell from the Makefile for sky130A so that the GPIO cell does not generate bit trash on the HVI mask due to remaining inconsistencies in the way the GDS for the cell is read into magic. Updated VERSION and also the required magic version for using this tech file (8.3.111), since only revision 111 will correctly handle the mask-hints method.
  Corrected the sky130 Makefile to put the special handling of the GPIO cell with "insert_property.py" below the installation of the library, or else the file to be modified won't be there. Corrected a handful of places in the common scripts where "/bin/env" was used instead of the more common "/usr/bin/env".
  Also: Added parameter handling in extraction of MOSFET devices for source and drain area and perimeter.
  Also: Changed the layer assignments for the fill layers to match what SkyWater expects. Added a fill layer generation and layers for local interconnect fill.
  
• posted: January 6, 2021 at 3:01am     version: 1.0     revision: 102
  Corrected the sky130_ef_io.gds file to correct the position of the overlay cell on the vccd_lvc_clamped2 pad. Updated the LEF files of the clamp-connected pads, which were out of date with respect to the GDS file.
  Once again edited the same clamp-connected pad layouts, this time to remove a metal wide-spacing DRC error caused by the additional metal1 connection to the back-to-back diodes.
  
• posted: January 5, 2021 at 3:00am     version: 1.0     revision: 101
  Initial None setting for tclscript to prevent referencing a non- existent variable later in the script. Merges pull request #88 from Ahmed Ghazy.
  
• posted: January 4, 2021 at 3:00am     version: 1.0     revision: 100
  Minor update which allows a custom Tcl script to be inserted in the GDS import script when generating magic cells. The script can then take advantage of the "flatglob" option to flatten specific cells on input, which can be used to work around database incompatibility issues when importing GDS into magic.
  
• posted: January 2, 2021 at 3:00am     version: 1.0     revision: 99
  Made a very minor change to the README file to reflect the new configuration option name "--enable-sky130-pdk" that replaces "--with-sky130-source"; plus I noticed that the README file also listed the incorrect option "--with-local-path" which should be "--with-sky130-local-path". No functional change was made to the repository.
  
• posted: December 31, 2020 at 3:01am     version: 1.0     revision: 98
  Modified the corner cell in the padframe corner overlay to add "obsactive" in the corner along with the existing "fillblock" to prevent the generation of fomfill in the corners, since the "fillblock" layer only blocks metal fill.
  Changed the magic tech file so that it recognizes "obsactive" and will translate it to an FOM waffle drop datatype, so that the change made to the corner pad in the last commit actually works as advertised. Rebuilt the custom pad extension GDS library with this change. Also corrected an error in the tech file where a missing comma would cause polysilicon not be recognized during fill pattern generation, leading to collisions between poly and poly fill shapes.
  Also: Removed the name "licon" from the magic techfile, as it is used incorrectly compared to the SkyWater documentation, and there is no concept in magic of a single contact type between local interconnect and poly, diffusion, or tap. Also changed some of the CIF names from the SCMOS naming conventions to SkyWater's; namely HVI instead of THKOX, NSDM instead of NPLUS, and PSDM instead of PPLUS. Hopefully this eliminates the worst inonsistencies and confusions.
  Also: Changed one instance of licon in the sky130.tcl PDK file to mcon.
  
• posted: December 30, 2020 at 3:02am     version: 1.0     revision: 97
  Added a full fill generation script which breaks a design up into tiles for faster, more memory-efficient processing. This includes some changes to the techfile to create two variants for the fill patterning, one that should be used for a full-chip pattern, and one to be used with the script. Also removed the patch file from yesterday's commit.
  Added the fill generation to the make script so that it gets installed in the magic setup section of the PDK.
  Also: Corrected one typo in the fill generation script.
  Also: Remove 0.015um met5 notch on {,dis}connect cells
  Also: Fill violating met1 holes in the clamp overlays
  Also: Update routing version of the IOs
  
• posted: December 29, 2020 at 3:01am     version: 1.0     revision: 96
  A number of changes to the magic techfile: (1) Added more mask-hints operators to the cifoutput section, to cover the ID layers, (2) merged the "sky130" and "vendorimport" styles of cifinput into a single style "sky130" with variants "sky130()" and "sky130(vendor)". This prevents mistakes caused by making changes to one of the styles while failing to make the corresponding change in the other, of which several exmples were discovered when doing the merge.
  Corrected one error with an overlay pad, which was colliding with via3s in different locations on one of the two cells it was being overlaid on, by creating a separate overlay cell for each pad. Corrected two other cells, one with the clamp overlay and one with just the power overlay, which used the wrong overlay cell.
  Also: Additional support for automatically searching standard places for repositories before attempting a download.
  
• posted: December 27, 2020 at 3:00am     version: 1.0     revision: 95
  First draft of a complete CDL/SPICE netlist for the sky130_ef_io cells (supplementary to sky130_fd_io). Previously these were black-box stub entries. Now they make references to the SkyWater cells, although those cells (or at least the SPICE netlists of them) are in the scratch repository and not yet pushed to the public repository.
  
• posted: December 25, 2020 at 3:00am     version: 1.0     revision: 94
  Changes from Donn to enhance the configuration script to allow specific tools to be enabled or disabled for setup installation.
  Changes to the techfile and netgen setup file in support of the sky130_fd_io I/O library; the area detection for areas of native Vt FETs was reduced from 1um to 0.35um because the former can overlap other areas and result in invalid transistor devices. The netgen setup added the I/O tap cell to the cells to exclude from matching (this change may be temporary).
  Also: Moved the fill type GDS import into the regular GDS import instead of in its own special section. Created new types for poly and FOM fill. Created type "fillblock4" to block all fill up to but not including metal5.
  Also: Updates from Donn to enable open_pdks to clone and install repositories as needed for the installation. Note change to configure script option for the path to the SkyWater PDK (if not being automatically installed in a local path).
  Also: Ran last commit from the wrong directory and didn't catch most of the modified files.
  Also: Corrected a comment line in the Makefile to match the text of the option in configure.
  
• posted: December 22, 2020 at 8:18pm     version: 1.0     revision: 93
  Corrected the netgen setup file, which was missing the nfet 5V native vt transistor in the list of transistors. Added an entry to ignore the cell "condiode", which appears in schematics but cannot be extracted (due to apparent lack of defining characteristics). Corrected a comment in the magic techfile (non-functional, no impact on use of magic).
  Added the netlist_to_layout python script that reads a SPICE netlist and creates a device generator Tcl script that can be run through magic to create all the devices, subcircuits, and ports as a starting point for a layout. This has just been dropped in without any attempt to integrate; it needs work to support both directory structure styles from open_pdks (EF_STYLE 0 or 1), and for the schematic checks and automatic netlist generation, needs to be switched from electric to xschem---which will have to wait on xschem integration in open_pdks (coming soon for sky130). The schematic tool independent part of this (SPICE to magic) needs to be split out as an option that can be called independently.
  Also: Restore I/O bus fillers from 0ad7fc94a
  Also: PAD GROUND -> PAD POWER
  Also: Remove leftover pin declarations in a clamped pad
  Also: Added ESD devices for the 5V nFET and pFET, which are essentially just marker layers used for LVS; however, as these are the devices with angled gates, they can be used
  Also: Added support in the magic tech file for ESD devices of the 5V nFET and pFET varieties. These are essentially just standard 5V FETs with a marker layer used for LVS purposes; however, as these are the devices with angled gates, they can be used to suppress DRC errors in the device layouts (which has not yet been done).
  Also: Reapply connect/disconnect cell fixes from fe967d6
  
• posted: December 21, 2020 at 3:01am     version: 1.0     revision: 92
  Added some devices to the sky130_setup.tcl file that had not been added to the netgen setup since they were added to the magic techfile extraction section.
  
• posted: December 20, 2020 at 3:00am     version: 1.0     revision: 91
  Added eight more overlay combination cells; these create connections between the clamp circuits and the buses as well as between the pad and buses. There are very many possible combinations, but these have been limited to a smaller set used for the caravel chip. Also updated the LEF views with magic 8.3.100, where a correction was made to an error that missed obstructions outside of the abutment bounding box when doing "lef write -hide". verilog netlists have been updated with the new combination cells. The CDL netlists have been updated with at least black-box views to assert pin order; and the full CDL netlist has been provided where the CDL exists for the cell in skywater-pdk-scratch (development build of sky130_fd_io).
  Forgot to update VERSION in the previous commit.
  Also: Ignore fill and tap cells in device level LVS
  
• posted: December 19, 2020 at 3:00am     version: 1.0     revision: 90
  Corrected the widespacing rules in the techfile so that they are triggered by metal width > 3um instead of metal width >= 3um.
  Added a filter to transform the sky130_ml_xx_hd library from metal1 to metal5 and scale the characters up by a factor of 12 so that they will be DRC clean for metal5.
  
• posted: December 18, 2020 at 3:00am     version: 1.0     revision: 89
  Added support for Paul Schulz's alphanumeric font character library for magic, including a modification of the text2mag.py script for use with the open_pdks installation.
  
• posted: December 17, 2020 at 3:00am     version: 1.0     revision: 88
  Updated the technology file to use the "requires" keyword, which will force magic to be updated to 8.3.99. Going forward, it will be much easier to deal with version requirements for magic when using the technology file, as the technology file can specify the version of magic required to use it. Also: Added the mask-hints operator introduced in magic 8.3.98. This allows automatically- generated mask layers to be supplemented by geometry specified as a cell property.
  Modified the magic tech file so that fill patterns are all generated on purpose 28 as specified by SkyWater.
  
• posted: December 15, 2020 at 3:00am     version: 1.0     revision: 87
  Added some exclusions for COREID areas to cifinput recipes that are copied up the hierarchy (to cope with composite layers being spread across different cells), as the core cells have contact cuts over space that cannot be distinguished from the above.
  
• posted: December 12, 2020 at 3:00am     version: 1.0     revision: 86
  Corrected the handling of POLYTXT and POLYPIN layers on GDS reads, so that a pin label over a gate does not overwrite the transistor with poly only.
  Added I/O pad clamp connection overlay cells to the I/O set. Updated a few rules for the GDS input of SRAM core cells, from a patch by Matt Guthaus.
  
• posted: December 11, 2020 at 3:00am     version: 1.0     revision: 85
  Added SITE and SYMMETRY entries for the sky130_ef_sc_hd__fakediode_2 LEF view.
  Add the other .lib needed to cover all HVL cells
  Also: [openlane] Parameterize the PDN configs even more
  
• posted: December 10, 2020 at 3:00am     version: 1.0     revision: 84
  Linking from None fix
  Updated VERSION to go along with the pull of the CI yaml file for CloudV.
  Also: Added types corenvar and corepvar to represent the ends of tap layers in the SRAM core cells that are tucked under poly and are not considered devices by SkyWater, but just extracted as parasitic cap. Note that the parasitic cap values for these layers still need to be specified in the extract section.
  Also: Corrected the sky130_ef_io.v verilog library to replace references to the deprecated cell sky130_fd_io__top_power_hvc_wpad with the replacement sky130_fd_io__top_power_hvc_wpadv2.
  Also: Added a fillblock shape in the corner of the I/O pad wrapper in sky130_ef_io so that the corner area with the alignment marking does not get covered in fill shapes during fill generation.
  Also: Generated GDS from the corner pad with fillblock after realizing that the installed file comes from the GDS, not the .mag file, so that changes to the .mag file are meaningless.
  Also: Revised one core locali rule that was modified yesterday that causes false-positive errors around contacts.
  
• posted: December 9, 2020 at 3:00am     version: 1.0     revision: 83
  Finalized (I hope) the fill generation output style.
  Corrected the configuration script to correctly handle an absent "dist-path". The previous syntax appears to be incompatible with some versions of bash.
  Also: Corrected the spacing rule for local interconnect in core cells (0.14um), and reverted back to the normal width and spacing rules for coreli because the edge4way rules are unnecessary, and just more confusing to the observer.
  
• posted: December 8, 2020 at 3:00am     version: 1.0     revision: 82
  Modifications to the waffle fill pattern generator output style.
  
• posted: December 4, 2020 at 5:11pm     version: 1.0     revision: 81
  Added a bare wirebond pad structure to the list of cells in the sky130_ef_io library.
  Modified the staging_install script so that an option "-variable" can be passed, such that .mag files in mag/ and maglef/ directories of the libraries will have GDS files point to the PDK by variable reference, e.g., using $PDK_PATH, so that layouts can be made portable.
  
• posted: December 4, 2020 at 3:00am     version: 1.0     revision: 80
  Corrected minor offsets in the metal positions of the special I/O bus connect and disconnect cells that were inherited from errors in the original spacer cells (that were fixed on the last commit).
  
• posted: December 3, 2020 at 3:00am     version: 1.0     revision: 79
  Modified the LEF views of the I/O padring filler cells so that they do not cover the empty area with the metal4 obstruction layer, which causes trouble with DRC and extraction if any active circuitry with wiring up to metal4 is placed in this area.
  Additional corrections to the magic and LEF views of the I/O cells to correct a minor error in positioning of one of the metal5 layers in the abstract view of the filler cells.
  
• posted: December 2, 2020 at 3:00am     version: 1.0     revision: 78
  Added tribuff_map to all standard cells
  Updated revision to go along with the latest pull request merge.
  Also: Changed the "lef" section of the techfile to cast via geometry in an obstruction section (other than vias/contacts below m1) to the base metal layer; otherwise "lef read" screws up the layers.
  
• posted: December 1, 2020 at 3:00am     version: 1.0     revision: 77
  Added tri-state buffer mapping file
  Updated tri-buf name
  Also: Updates needed for the tristate buffer mapping
  Also: control the global_connections section in common_pdn.tcl with a flag
  Also: Updated the revision to go along with recent pull request merges.
  
• posted: November 30, 2020 at 3:00am     version: 1.0     revision: 76
  Added option to the poly resistor to use a high-voltage well for the guard ring.
  Modified PPLUS and NPLUS layer generation operators in the cifoutput section of the magic tech file, as they were missing the grow/shrink operators needed to merge across narrow gaps.
  
• posted: November 28, 2020 at 3:00am     version: 1.0     revision: 75
  Corrected rule poly.9 so that it is not flagged by type "rmp", which is POLY + POLYSHORT, and not POLY + POLYRES, which is what the rule refers to. This prevents false positive errors in the standard cell tap cells, which contain the poly short layer.
  Corrected misspelling "php" to "pnp" in the netgen setup, as pointed out by @yrrapt in github issue #66.
  Also: Corrected the MiM cap rules (some of which were more conservative than necessary because the via surround and spacing rules had not been corrected for the amount of surrounding metal already included in the contact type). Also corrected the Makefile so that it does not fail on attempting "rm -f" on a directory.
  Also: Corrected rule cap2m.8, as it implies that stacked MiM caps may not overlap contacts---which essentially makes them not able to stack. . .
  Also: Removed the rndiff, rpdiff spacing to contact rules, which do not exist in the PDK (required distance is zero; i.e., no overlap, which is enforced by the definition of the magic tile types).
  Also: To go along with the last commit, diffusion resistors must be included in the types that can satisfy the surround rule for diffusion around licon. Also corrected an error in which mvpdiffres was not in the list of types checked for MV diffusion width.
  Also: Revised the code that generates MiM caps in the PDK Tcl scripts, because the DRC rules specifically prevent cap2m overlapping via3; so to make an actual stacked capacitor, the contacts for the lower cap cannot be directly under the first. So the options have been enhanced to allow the contact to the MiM caps to only partially cover the capacitor plate area. Also decreased the spacing from cap plate to contact to the minimum required, and added code to increase that distance as necessary to enforce the minimum metal spacing rule on the capacitor top. Also updated the extraction rule for the diffusion resistor types to match the added subcircuit definitions for both.
  
• posted: November 25, 2020 at 3:00am     version: 1.0     revision: 74
  Add custom I/O wrapper and bus slices (fillers)
  Install fakediode properly
  Also: Add antenna info for sky130_ef_io pads
  Also: Update no_synth.cells
  Also: Update openlane pdngen config
  Also: Updated version to 1.0.73 to go along with the pull request merges.
  
• posted: November 24, 2020 at 3:00am     version: 1.0     revision: 73
  Added the layouts used for DRC ruleset development to sky130/custom/drc/.
  Corrected the "short" model which is actually being called as a subcircuit, not a resistor, from the extraction in magic. Also added a new custom file "diode.spice" which does the same thing for the diodes, which are defined as low-level diode types but are extracted from magic as a subcircuit.
  Also: Corrected "corelocali" layer rules so that magic does not raise various false positive errors when using the layer around contacts and diffusion.
  
• posted: November 23, 2020 at 3:00am     version: 1.0     revision: 72
  Added a new script in common/ "cleanup_unref.py" which removes all parameterized cell layouts from a directory that are unreferenced by any other layout file. These "orphan" cells are commonly left behind when changing parameter values of parameterized cells.
  Corrected the position of "suspendall" in the contact generation routines in the PDK Tcl file for magic, so that those routines do not return while still in the "suspendall" state.
  Also: Corrected magic extraction rule for the high-resistance poly resistors, which are specific to the device width and therefore do not need or take a value W. Corrected a typo in the names of the 5V FETs in the netgen setup file.
  Also: Corrected all of the contact and via drawing routines to get the proper overlap of each layer.
  
• posted: November 22, 2020 at 3:00am     version: 1.0     revision: 71
  Corrected the PDK units conversion, which was using floor() instead of round() and resulting in incorrect units. Corrected the sonos device, which was failing generation if the guard ring was not selected. Added options to all devices to generate vias on top of the contacts, since it is especially important in the SkyWater technology to get above the high-resistance local interconnect layer.
  Updated the version number and corrected a typo preventing vias from being generated on a guard ring's left side.
  Also: Corrected another minor error affecting the position of vias on the left and right sides of the guard rings.
  
• posted: November 21, 2020 at 3:00am     version: 1.0     revision: 70
  Corrected latchup DRC rules for nwells to include the special pnp layer for the pnp transistor base, so that it does not flag a false positive error.
  
• posted: November 20, 2020 at 3:00am     version: 1.0     revision: 69
  Corrected misspellings of device model names as pointed out by Matt Venn in issue #59 on github.
  Corrected misspellings of device model names as pointed out by Mitch Bailey in issue #59 on github.
  
• posted: November 19, 2020 at 3:00am     version: 1.0     revision: 68
  Reworked the THKOX (HVI) layer output generation rules; it now generally does the right thing, and flags problematic areas; a few such problematic areas are false positives.
  
• posted: November 18, 2020 at 3:00am     version: 1.0     revision: 67
  Change to the magic techfile to more properly handle the THKOX layer on GDS output; this removes some odd artifacts from the output, but there are still some issues (maybe only one?) that are still being debugged.
  retry on skywater-pdk conda-env fetch fail
  Also: add building the hvl library to the test cases
  Also: update skywater pdk commit hash
  Also: reduce the required size for passing
  Also: Updated version to go along with the pull request and other changes made locally.
  
• posted: November 17, 2020 at 3:00am     version: 1.0     revision: 66
  Changed the Makefile.in file so that it sets the "version" value in the Magic techfile to the result of "git describe --long", so that instead of updating the techfile version whenever I think about changing the revision value in the Makefile, it updates automatically.
  
• posted: November 16, 2020 at 3:00am     version: 1.0     revision: 65
  Modified the seal ring abstract view so that it shows as DRC clean under DRC style "drc(full)". Updated the magicrc file to default to MAGTYPE = "mag", as there are few reasons other than standard cell layouts to use "maglef" type.
  
• posted: November 15, 2020 at 3:00am     version: 1.0     revision: 64
  Corrected the other cifinput style (vendorimport) with the same additions for handling the special FET types in SRAM core cells as was done in the previous commit.
  
• posted: November 14, 2020 at 3:00am     version: 1.0     revision: 63
  Revised the rule for checking (effectively) HVI to nwell spacing. This must use a cif-drc rule because the chech needs to be to LV nwell, not HV nwell (which would have merged the HVI layer). Otherwise there are lots of false positive errors.
  Modified the definition of device ppu to include HVTP, as otherwise the SRAM core cell pFET gets interpreted as a pFET-HVT, which does not have the right model bins for the SRAM device.
  Also: Corrected the GDS read-in so that it correctly separates out the "npass" (smaller) device from the "npd" device.
  Also: Removed redundant extraction entries for two of the nFET devices (this change does not affect behavior in any way, as redundant entries are ignored).
  Also: Modified DRC rule for li to allow 45 degree angles inside the SRAM core cell. This is sort of a moot point, given all the ways normal DRC is violated inside the SRAM core, but whatever.
  
• posted: November 13, 2020 at 3:00am     version: 1.0     revision: 62
  Added a missing DRC rule for poly to HV-diffusion spacing.
  Added additional rules for HV nwell spacing, taps without contacts, and minimum tap area to satisfy the minimum PPLUS/NPLUS implant area rule.
  Also: Added additional rule for HVNTM spacing, especially for nhvnative transistors with a p-tap between them.
  Also: Moved two DRC-CIF rules out of the drc(fast) variant because that triggers all of the CIF layers to be generated and slows things way down.
  
• posted: November 12, 2020 at 3:00am     version: 1.0     revision: 61
  Modified foundry_install.py to add SPICE/CDL port index annotation to the generation of maglef files (which was done for layout views in mag/ but had been missed for layout views in maglef/). Also: Corrected a regexp for port labels that failed to match on labels with a sticky bit set, which was causing port numbering to get screwed up after being carefully set by the generation scripts. Thanks to Mitch Bailey for the fix.
  Updated the sky130/README file to include adding sky130_fd_io as a submodule, since that is now available in the skywater-pdk repository.
  Also: Corrected rules for poly spacing to poly resistor, which was causing false positive errors on mrp1 and pres resistors (the non-high-res resistors).
  Also: Corrected minor typo in the last commit.
  Also: And one more typo fixed.
  
• posted: November 9, 2020 at 3:00am     version: 1.0     revision: 60
  remove the script itself, since it's no longer needed
  Update openlane PDN config
  Also: Updated version to go alonge with the last two pull request merges.
  
• posted: November 8, 2020 at 3:00am     version: 1.0     revision: 59
  Corrected typos that crept into the MiM2 cap section after copy and paste from the MiM cap section, in the magic techfile.
  
• posted: November 7, 2020 at 3:00am     version: 1.0     revision: 58
  Removed the "cellname delete \(UNNAMED\)" commands from the generate_magic.tcl scripts, because this is causing a database corruption in magic. This is a "quick fix", as the nature of the database corruption needs to be investigated. This fix prevents apparently unrelated errors in the port indexing in the installed files in the library mag/ directories.
  
• posted: November 4, 2020 at 8:37pm     version: 1.0     revision: 57
  Changed seal ring generator to round up widths on layouts with odd-numbered lambda units; rounding down causes a tiny gap in the middle of the seal ring edges. Added angle restriction rules to the magic techfile.
  Corrected another couple of errors where EFS8A was referenced in the seal ring generator script instead of sky130A.
  Also: Removed the call to script fix_missing_diodes_lef.py, because the issues has purportedly now been fixed in the skywater-pdk repository.
  
• posted: November 4, 2020 at 3:00am     version: 1.0     revision: 56
  Corrected errors related to the standard cells and the DRC rules for several of the FET devices with HVT/LVT implants. Also corrected the missing extraction device for type "rmp", and removed unused options from the "device resistor" lines.
  Corrected a problem in the last commit in which an extra block of text in the magic techfile got accidentally copied and pasted.
  
• posted: November 3, 2020 at 3:00am     version: 1.0     revision: 55
  Changed the OSU library "rename" to include the (nonstandard) ".tlef" extension. Also, noting that the check for names after "rename=" that do not have file extensions is incomplete, added a case for "techlef" and a catch-all case at the end. This commit effectively implements Amr's pull request #46, but in a slightly different way.
  Updated VERSION to go along with the last commit.
  
• posted: October 30, 2020 at 3:00am     version: 1.0     revision: 54
  Finally corrected all of the eight diode types, which had a lot of typos left over from the conversion from s8 to sky130.
  Modified the OSU install so that sky130_osu_sc.tlef gets renamed to sky130_osu_sc_t18.tlef. This happens internally to foundry_install.py
  
• posted: October 29, 2020 at 3:00am     version: 1.0     revision: 53
  Added the npn_11v0 devices to the extraction types. Note that the 11V NPN looks like a mashup of an NPN and extended-drain FETs, and extracts that way, requiring a change to magic (not done yet) that can tell the extraction to ignore certain devices.
  Added handling of the 11V NPN and corrected for the problem of extracting the additional implicicit FET devices that are part of the NPN. This requires the latest version of magic (8.3.73) or else a device called "Ignore" shows up in the SPICE output.
  Also: Removed parameters from the ignored devices, as that is irrelevant additional information.
  Also: Replaced all the "s8" references in the custom seal ring generator scripts to "sky130".
  Also: Corrected the sky130.tech file for the required tap surrounding an LICON contact (which is zero on two sides); the rule for "diff" surround should be interpreted as meaning "diff" and not "tap".
  Also: Add openlane configs related to the I/O library
  Also: PAD GROUND -> PAD POWER
  Also: Corrected some errors in the diode parameterized cells that did not get cleanly converted from s8.
  
• posted: October 25, 2020 at 3:00am     version: 1.0     revision: 52
  Corrected outdated references to "s8" in the README.md file.
  Updated README.md with more complete instructions that will show up on the github page.
  
• posted: October 23, 2020 at 3:00am     version: 1.0     revision: 51
  base commit for travisCI auto testing
  Updated VERSION to go along with the travis-ci additions from the github pull request.
  
• posted: October 22, 2020 at 3:00am     version: 1.0     revision: 50
  fix the swapped lines in fix_missing_diodes_lef.py
  Updated VERSION along with the two pull request merges.
  Also: Fixed problem with regexp in the netgen setup not ignoring decap and fill cells for any library not having a 2-character designator after "sky130_fd_sc_", as pointed out by Mitch Bailey in issue 37.
  Also: Provisional additions of under-bump material and redistribution layer vias (testing whether these layers can be derived or need to be explicitly drawn).
  
• posted: October 21, 2020 at 3:00am     version: 1.0     revision: 49
  sky130: add support for sky130_osu_sc_t18
  Another few follow-up corrections.
  Also: Updating VERSION to go along with the git merge of the most recent OSU stuff.
  Also: openlane config updates (PR #30 and #31):
  Also: add WIRE_RC_LAYER to the common config.tcl
  Also: base commit for the lef modifying scripts
  Also: fixes
  Also: a lame solution to make sure you don't invalidate the lef (do the same thing twice)
  Also: cleanups and using hs/ms diodes in openlane
  Also: cleanup according to the reviews
  Also: Refer to the issue in a comment
  Also: Modified a number of scripts using "/bin/env" to make it "/usr/bin/env", since the "/bin" location does not exist on some versions of Linux.
  
• posted: October 18, 2020 at 3:00am     version: 1.0     revision: 48
  Corrections in the magic techfile for the PPLUS and NPLUS auto-generated layers, especially to avoid bridging across butted taps.
  Corrected and updated about half of the known missing/incorrect rules in the DRC ruleset.
  Also: Finished pass through the DRC rule templates and fixed all of them that I could determine how to fix, leaving only a handful of errors not handled correctly.
  
• posted: October 15, 2020 at 3:00am     version: 1.0     revision: 47
  Corrected the tab error in cdl2spi.py, and modified foundry_install.py to make use of LEF and "readspice" annotation when creating layout database files from GDS sources.
  Corrected the Magic device generator to paint nwell under pFETs when the guard ring is not selected (previously it was drawn with the guard ring so went missing when the guard ring was unselected). Corrected MiM cap DRC rules (to match the Calibre decks rather than the documentation, which has different layers for MiM cap). Note that Magic was modified to correct a wrong reported distance on CIF-DRC rules such as the one used for one of the MiM cap rules.
  
• posted: October 14, 2020 at 3:00am     version: 1.0     revision: 46
  Revised the install script for the released public repository for the I/O library sky130_fd_io. This mostly involved deleting files from the custom addition library, most of which need to be put back at some point with the new naming scheme.
  Filled in additional files for the sky130_ef_io overlays and additional cells.
  Also: Updated cdl2spi.py to handle resistors with models specified normally and not with $[...].
  
• posted: October 8, 2020 at 3:00am     version: 1.0     revision: 45
  Modified the cifinput section of the magic techfile to always draw pwell under p-tap (TAP AND-NOT NWELL). This serves to ensure that abstract views made with "lef write -toplayer" have the pwell masterslice layer to ensure the correct connectivity between the power and ground rails and the well and substrate, respectively.
  
• posted: October 3, 2020 at 3:00am     version: 1.0     revision: 44
  Corrected capacitor extraction (needed type "csubcircuit" and not "subcircuit" to get the correct L and W calculation).
  Corrected some errors in the netgen setup, including incorrect references to circuit1 vs. circuit2, and specifically ignoring the monte carlo parameters "nf" for transistors and "mf" for MiM capacitors.
  
• posted: October 1, 2020 at 3:00am     version: 1.0     revision: 43
  Moved sort_pdkfiles.py to common/, and modified behavior to always use the default sort (which is a natural sort), given that doing "glob.glob" on a file directory results in a pretty arbitrary and meaningless ordering.
  
• posted: September 26, 2020 at 3:00am     version: 1.0     revision: 42
  Added additional option "sort" to supply a sorting script to specify the order of files when compiled into a library; this allows the Makefile to enforce natural sort order and/or put dependent entries at the top. Also added a custom script for sky130 to handle the assortment of "include" statements in the standard cell verilog before generating the library files.
  openlane support for latch mapping in synthesis
  
• posted: September 25, 2020 at 3:00am     version: 1.0     revision: 41
  Various modifications to accommodate the somewhat complicated management of include statements in verilog files in order to build the compiled libraries.
  
• posted: September 23, 2020 at 3:00am     version: 1.0     revision: 40
  Modified the techfile to make use of a techfile extension added to magic that allows the paint/erase lines in "compose" to declare multiple types to be painted. This allows the "obslic" contact to be erased if painted over with obsm1 without erasing obsli underneath.
  One more addition to the magic techfile, to make metal1 electrically connected across obslic, which is only supposed to represent an obstruction on the lower (locali) layer.
  
• posted: September 22, 2020 at 3:00am     version: 1.0     revision: 39
  Added resistor type short as a custom modification to the device models. Changed "obslic" (li-m1 contact as an obstruction layer) to be defined not between obsli and obsm1, but between obsli and metal1. This is consistent with the use of obsli in the standard cells with the LEF files generated using the "-toplayer" option, and allows metal1 to be placed across the power rails and obslic contacts without generating DRC errors.
  Corrected the names of the mrdp_hv and mrdn_hv devices to match the sky130_fd_pr names, and made them resistor types rather than subcircuit types, to match the model definitions.
  
• posted: September 21, 2020 at 3:00am     version: 1.0     revision: 38
  First cut at properly incorporating the sky130_fd_pr primitive devices (much work do be done still).
  Updated VERSION along with sky130_fd_pr library changes
  Also: 2nd pass at updating the sky130 installer for sky130_fd_pr.
  Also: There are continued problems with simulating various devices, but the installation is generally correct.
  Also: Messed with the MiM cap definition before finally determining that the real problem is the same as the failure to compute W and L correctly for extended drain devices; i.e., the algorithm is wrong with the terminals are on a different plane.
  
• posted: September 18, 2020 at 3:00am     version: 1.0     revision: 37
  Corrected the DRC rule checking for metal1 hole area. It was not counting obstruction metal layers as part of the metal layers, and so was ending up flagging thousands of errors in the power rails of the standard cells, where the contacts (to li) were placed on obstruction layers as part of the "lef write -toplayer" option. This would only show up when using "drc(full)", which runs the minimum hole area check.
  
• posted: September 17, 2020 at 3:00am     version: 1.0     revision: 36
  Removed a lot of locks on layers, leaving mostly just obstruction and fill layers. Changed the names used for the DRC rules to match the names used in the Google/SkyWater online documentation.
  Corrected one typo in the techfile.
  Also: Corrected a typo in the magic techfile.
  
• posted: September 12, 2020 at 3:00am     version: 1.0     revision: 35
  Corrected the area parameter passed to the bipolar devices in the magic techfile, matching an update to magic to correct the area output for terminals other than the device identifier.
  
• posted: September 11, 2020 at 3:00am     version: 1.0     revision: 34
  Substantially revised the technology file for magic, the PDK device generator script for magic, the setup file for netgen, and the DRC torture test generator, to match the final naming conventions for the sky130_fd_pr library of primitive devices.
  
• posted: September 10, 2020 at 3:00am     version: 1.0     revision: 33
  Added support for the OSU standard cells for sky130 based on the existing repository.
  Modified the spectre_to_spice.py script to remove a specific use of "m" in expressions, which might be incorrect to begin with.
  Also: Added support for bipolar transistor types (using the pwell or nwell base layer as the transistor ID type) and bipolar transistor extraction.
  Also: Added preliminary support for extended drain devices (reading and extraction).
  Also: Finished implementing the three types of 20V extended drain devices (for reading and extracting; writing not yet supported).
  
• posted: August 31, 2020 at 3:00am     version: 1.0     revision: 32
  Split the cifinput section into two, because SkyWater sources have totally confused text and pin purposes in the GDS files, and need to have a style that maps both purposes onto "port".
  openlane configs updates
  Also: all common_pdn.tcl configs are now configurable
  Also: renamed variables to follow the conventions
  Also: Updated VERSION to go along with the last pull request.
  
• posted: August 29, 2020 at 3:00am     version: 1.0     revision: 31
  Additional changes/corrections to the spectre_to_spice script.
  
• posted: August 28, 2020 at 3:00am     version: 1.0     revision: 30
  More changes to the spectre_to_spice.py code.
  Added find_all_devices.py from the Google/SkyWater work, as it is a useful script for determining information about where a subcircuit can be found in a model directory hierarchy, although it is somewhat tied to the Google/SkyWater specific file hierarchy.
  
• posted: August 26, 2020 at 3:00am     version: 1.0     revision: 29
  Corrections, mostly to spectre_to_spice to handle various issues, especially with the use of primitive device prefixes 'C' and 'R' to call subcircuits.
  
• posted: August 20, 2020 at 3:00am     version: 1.0     revision: 28
  Added a new script "fix_subckt_params.py" which works with the spectre_to_spice.py script, and moves parameters from a .param block in a subcircuit up to the .subckt line, so that the parameter can be passed to the subcircuit.
  Added a script that parses a SPICE file and prints the parameters that are on the .subckt line, and the parameters that are internal to the subcircuit in a .param statement. Also, corrected spectre_to_spice.py to not add braces around an expression that is already encapsulated by single quotes, as that causes grief to ngspice.
  Also: Forced spectre_to_spice.py to translate spectre model types "resistor" and "r2" to SPICE semicondutor resistor model type "r". The former is almost certainly correct; the latter, I'm unsure of.
  
• posted: August 18, 2020 at 3:00am     version: 1.0     revision: 27
  Added "split_one_spice.py", a companion script to "spectre_to_spice.py" that splits up a SPICE file (output from "spectre_to_spice.py") that has multiple subcircuits in it into multiple files, one file per subcircuit. This is much like "split_spice.py" except that is does not try to break models out of subcircuits, and it is much more careful about placing global parameters with the subcircuits that use them, and finding global parameters and other parts of the file that are common to more than one of the subcircuits, and retaining them in the original file.
  
• posted: August 15, 2020 at 3:00am     version: 1.0     revision: 26
  Started the conversion of device model names to the new naming convention on the Google/SkyWater repository.
  
• posted: August 13, 2020 at 3:00am     version: 1.0     revision: 25
  Updated the magic techfile with the first draft of the completed automated waffle fill cif output style.
  
• posted: August 10, 2020 at 3:00am     version: 1.0     revision: 24
  Modified the magic device generator to properly handle the "nf" parameter on MOSFET devices when converting from a netlist to layout. Corrected the netgen setup to ignore both "nf" and "mult" as netlist parameters, as well as other non-critical parameters that may or may not appear in both the schematic and layout- extracted netlists.
  Corrections to the device generation script and magic techfile to support the specific-width xhrpoly and uhrpoly devices.
  Also: More corrections to spectre_to_spice.py and split_spice.py.
  Also: Made small whitespace fixes per contents of pull request #23 by Tim Ansell.
  
• posted: August 9, 2020 at 3:02am     version: 1.0     revision: 23
  Continuation operator needed in sky130/Makefile.in
  Seems that some changes (SRAM devices added to netgen setup)? were not committed previously?
  Also: Updated revision to trigger tarball and github mirror on new commits.
  
• posted: August 6, 2020 at 3:00am     version: 1.0     revision: 22
  Modified the configuration file to better handle the installation options. In particular, removed the "install-local" and "install-dist" targets in favor of just using "make install", with the install type dependent on the choices made by "configure". Made the local and distributed install paths specific to the PDK. Added the link type and efabless-style to the configuration options. Added a list of generic standard cell gates to be used by (not yet posted) software to automatically generate digital symbol libraries.
  Updated revision to force a new tarball and the github mirror.
  Also: Corrected the handling of parameters inside and outside a subcircuit call.
  
• posted: August 3, 2020 at 3:00am     version: 1.0     revision: 21
  OpenLane support for other sky130 variants
  Renamed some variables to more meaningful names
  Also: Minimal set up for autotools
  Also: Updated the README files to reflect the new use of the autoconf "configure" script, and updated the VERSION revision number.
  
• posted: August 2, 2020 at 3:00am     version: 1.0     revision: 20
  Changed "convert_spectre.py" to "spectre_to_spice.py". Corrected the script to properly identify weird "spectreisms" in which resistors or capacitors are prefixed as subcircuits with "x" but use a model which is a resistor or capacitor. Also: Added more handling of SRAM (coreid) layers in the magic techfile for support of OpenRAM, and added a first pass at fill pattern generation in magic.
  Additional fix to spectre_to_spice.py to handle spectreisms.
  Also: Updated revision to trigger new tarball and github mirror.
  
• posted: August 1, 2020 at 3:00am     version: 1.0     revision: 19
  Updated the magic techfile to correct a few errors and extend the support for SRAM cells (to read and extract; no attempt to try to write an SRAM cell correctly).
  
• posted: July 29, 2020 at 3:00am     version: 1.0     revision: 18
  Updated the convert_spectre.py script to correct a number of errors, especially related to CDL formats which may appear in spectre files. Added a "split_spice.py" script to take the output of "convert_spectre.py" and pull the subcircuit definitions out of it and put them in separate files.
  More fixes on the two spectre-to-SPICE conversion scripts.
  Also: Enabled the REDISTRIBUTION option in the Makefile for sky130A. Corrected the convert_spectre.py to ignore .scs files, which have no SPICE equivalent.
  
• posted: July 28, 2020 at 3:00am     version: 1.0     revision: 17
  Corrected the Makefile to correct the string used for excluding files from the LEF compile.
  Setting the default LINK_TARGETS to none
  Also: Minor typos fixed in the Makefile
  Also: Minor fixes to the magicrc and netgen setup files
  Also: Removing the :: from ::env because I normally don't like to force the scope of commands in Tcl, which causes problems if you try to rename the command. Although its use here is probably harmless, I find the notation cumbersome.
  Also: Removed ; after END LIBRARY
  Also: Added a comment about EF_STYLE in sky130/README
  Also: Commented out missing IO and OSU libraries
  Also: Using TECHNAME in klayout .lyt file
  
• posted: July 27, 2020 at 3:00am     version: 1.0     revision: 16
  Removed all of the routines that generate compiled libraries from individual files for various file formats (GDS, LEF, SPICE/CDL, and verilog (liberty is unfinished and probably never will be), and put the in individual files that can be either run separately from the command line or included into the foundry_install.py script and run internally.
  Additional corrections to the standalone library compile scripts.
  Also: Added the "END LIBRARY" line back to the end of the LEF library after removing all of the individual ones.
  
• posted: July 26, 2020 at 3:00am     version: 1.0     revision: 15
  Fix for naming conventions (only comments changed).
  
• posted: July 24, 2020 at 3:00am     version: 1.0     revision: 14
  Finished the first working draft of the spectre-to-SPICE conversion script.
  
• posted: July 23, 2020 at 3:00am     version: 1.0     revision: 13
  Added a convert_spectre.py script which makes a basic first-pass attempt to convert spectre files into valid SPICE files. Note that this does not attempt to guarantee ngspice compatibility, as that is handled by other scripts.
  
• posted: July 21, 2020 at 3:00am     version: 1.0     revision: 12
  Per the bug report by Ronan Barzic, corrected the staging_install.py script to correctly support LINK_TARGETS=none.
  
• posted: July 18, 2020 at 3:00am     version: 1.0     revision: 11
  Corrected the last commit where I accidentally inserted a tab, discovered by Sylvain Munaut (whose pull request I am improperly bypassing, sorry).
  
• posted: July 17, 2020 at 3:00am     version: 1.0     revision: 10
  Changed the "create_gds_library" command to use the new command option "gds library" in magic, so that the top level with the example cells is not saved into the GDS output (which can cause problems with some tools).
  
• posted: July 16, 2020 at 3:00am     version: 1.0     revision: 9
  Modified sky130.tech magic techfile to add nwell and pwell as masterslice layers to the LEF input setup; this should resolve issues with the VNB and VPB pins in standard cells. Along with that, committed a script to correct the layers assigned to VNB and VPB in the original sources.
  
• posted: July 15, 2020 at 3:00am     version: 1.0     revision: 8
  Corrected the Makefile, which was using the "exclude" option on the standard cell verilog that was supposed to be used on the standard cell LEF. Mostly all this does is to change the nature of the error that occurs. Ultimately the source of the LEF files needs to be fixed, which will happen eventually. Also corrected the generate() routine in soc_floorplanner. This fixes the behavior in which clicking on the "Generate" button in the floorplanner app causes an error.
  
• posted: July 14, 2020 at 3:00am     version: 1.0     revision: 7
  Corrected the surround rule for metal4 around via3 in the DRC and wiring sections. It had been implemented as 0.060 / 0.065 (directional) instead of 0.065 (regardless of direction).
  Removed the diode cell CDL files for sky130_fd_sc_hd, which are currently in the Google/SkyWater repository.
  
• posted: July 12, 2020 at 3:00am     version: 1.0     revision: 6
  Corrected sidewall values for poly through metal2, which had been missing from the original simulation.
  Updated README to correct the instructions for the Google/SkyWater repository install (had the wrong names for the library subdirectories).
  
• posted: July 11, 2020 at 3:00am     version: 1.0     revision: 5
  Corrected all of the parasitic capacitance values in the tables based on the values and equations in the SkyWater Calibre PEX decks, and verified by extracting an example with exhaustive combinations of overlapping poly, local interconnect, and metal layers.
  
• posted: July 9, 2020 at 3:00am     version: 1.0     revision: 4
  Minor corrections in the openlane configs
  Corrected the names of the various digital standard cell libraries in the README file (which had become scrambled).
  Also: Added Apache 2.0 license file.
  Also: Added additional license information to the README files.
  Also: Removed the custom technology LEF files, as these have been added to the Google/SkyWater git repository. Added more complete instructions for cloning and installing the Google/SkyWater repository. Modified the Makefile and qflow setup file for use with the technology LEF files from the repo.
  
• posted: July 8, 2020 at 3:00am     version: 1.0     revision: 3
  Reorganized the top level so that most working files for EDA tool setup are in directories with the EDA tool name. Updated the openlane setup files.
  Updated version to update website and the github mirror repository.
  Also: Added support for the OSU standard cell set for sky130, based on the existing repository.
  Also: Added back the qflow support for the OSU standard cell libraries.
  
• posted: July 7, 2020 at 3:00am     version: 1.0     revision: 2
  Added "distclean" target to the Makefile, which is expected by the scripts handling automatic updates to the tarball and website.
  Corrected variable reference in the README install instructions.
  
• posted: July 6, 2020 at 3:00am     version: 1.0     revision: 1
  Updated version to force an update on the system, and to force a mirror copy to github overnight.
  
• posted: July 5, 2020     version: 1.0     revision: 0
  First public release.

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Last updated: January 9, 2021 at 3:01am