Table of Contents

Revision information on Open_PDKs 1.0

Revision information on Open_PDKs 1.0:

Open_PDKs revision history: Version 1.0

• posted: August 12, 2022 at 2:00am     version: 1.0     revision: 323
  Added code to fix_digital_lef.py to correct the LEF class of the diode antenna cells to "CLASS CORE ANTENNACELL", for all digital standard cell libraries.
  Forgot to update the version number with the previous commit.
  
• posted: August 2, 2022 at 2:00am     version: 1.0     revision: 322
  Added GF180MCU support. Corrected the foundry_install script to handle the check for a GDS file having a top level (vs. being a library) inside the Tcl script. Updated the reference library commit numbers for sky130 and gf180mcu. Added missing entries for the xschem, precheck, and klayout third-party libraries to the nodeinfo.json file for sky130. Corrected the script used by "make reference", which was still expecting the original keyword "distribution" instead of "reference".
  
• posted: July 30, 2022 at 2:00am     version: 1.0     revision: 321
  Config Updates + Magic Update
  Updated VERSION after merging pull request #267. Edited the asynchronous (extended-drain) devices in the netgen config file to change the width tolerance from 7% to 1%, since the 7% value got copied up from the ESD FET devices below, where the higher tolerance is needed to account for the difference in interpretation of device width where there is a flanged gate on the device layout.
  
• posted: July 29, 2022 at 2:00am     version: 1.0     revision: 320
  Updated the sky130 Makefile to separate the LEF libraries for the sky130_fd_sc_hd__* macros and the sky130_ef_sc_hd__* macros.
  Updated the VERSION to go along with the sky130 Makefile change.
  Also: Modified the netgen setup for sky130 per Mitch Bailey's observation that the 16V and 20V devices are extended-drain devices and so should not be allowed to permute source and drain terminals.
  
• posted: July 26, 2022 at 2:00am     version: 1.0     revision: 319
  A few minor corrections to the netgen setup file to remove a comment that does not apply to sky130, and to set the "devices" variable back to a null list before the ESD device processing so that the standard FETs do not get processed twice. Both changes have no effect on PDK and tool functionality, but makes the code cleaner and more correct.
  
• posted: July 24, 2022 at 2:00am     version: 1.0     revision: 318
  Made a correction to the "create_gds_library.py" script, which was making the unsupportable assumption that a GDS cell name is the same as the file name without the extension. Changed the script to have magic query all the top level cell names and use that list to generate the single library of all cells.
  Corrected the liberty library file generator script to avoid failing on blank lines.
  Also: Reverting the configure script for the sky130 process, as I accidentally pushed a version that references an additional PDK that does not exist, which would require people to run autoconf to get back the original configure script.
  Also: Made another correction to the create_lib_library python script, due to the "flexible" allowed syntax rules for whitespace in liberty files.
  Also: Fix a few places we modify the techlef and don't mark it modified
  Also: sky130B missing MINENCLOSEDAREA
  Also: Merged pull requests #260 and #262 from Anton Blanchard
  
• posted: July 3, 2022 at 2:00am     version: 1.0     revision: 317
  add n-well generator
  Modified the nwell-drawing code from the device generator provided by Pepijn de Vos (pull request #259) to make the diffusion extents and nwell surround minimum for the technology.
  Also: Corrected the "sed" script for installing the xschem test circuits file for variant sky130A, as recommended by Stefan Schippers to prevent errors resulting from incorrect changes to the ReRAM components.
  Also: Corrected a variable misspelling in create_lib_library.py
  
• posted: June 28, 2022 at 2:00am     version: 1.0     revision: 316
  Corrected the sky130 JSON file to add a couple of missing commas that break JSON syntax.
  
• posted: June 21, 2022 at 2:00am     version: 1.0     revision: 315
  Fixed the sky130 Makefile, which recently accidentally got committed with a recipe intended for the continuous models, which exist only in a private repository. The error prevents open_pdks from building and installing libs.tech/ngspice/.
  
• posted: June 17, 2022 at 2:00am     version: 1.0     revision: 314
  Updated the klayout installation to take its contents from the 3rd party repositories at Efabless and Mabrains, avoiding the necessity of maintaining local versions of the klayout setup and scripts for sky130.
  
• posted: June 8, 2022 at 2:00am     version: 1.0     revision: 313
  Fix a couple of typos in the klayout DRC deck
  Updated version with the merge of pull request #256 from Anton Blanchard.
  
• posted: June 5, 2022 at 2:00am     version: 1.0     revision: 312
  Updated the OpenRCX rules based on the new magic handling of fringe capacitance over an area of effect, and nearest-neighbor edge searches that block shielded shapes behind. The fringe capacitance over area produces non-zero values now for wires at a diagonal position with overlap, and correctly pro-rated values for wires with underlap. All values in the tables have dropped significantly, probably mostly due to better modeling of the sidewall coupling to match the tabular data from SkyWater.
  
• posted: May 29, 2022 at 2:00am     version: 1.0     revision: 311
  Corrected an error in the foundry_install script that duplicates the "lef read" line in the script to generate views using magic, resulting in duplicate macros in the LEF library file.
  Corrected an issue in foundry_install.py that will remove a LEF library before it can use it for annotation if there is only one LEF library file in the vendor source.
  
• posted: April 19, 2022 at 2:00am     version: 1.0     revision: 310
  Changed the extraction declaration for varactor devices (*_cap_var_*) in the magic tech file so that it properly extracts the substrate as the bulk terminal, instead of the nwell. Also removed the output of source and drain area and perimeter, as those are not used by the device model.
  Corrected the GDS output and input for the ReRAM layer which was, in a nutshell, all screwed up.
  
• posted: April 15, 2022 at 2:00am     version: 1.0     revision: 309
  Add a primitive OpenRCX configuration based on spef_extractor
  Updated version to go along with the merge of pull request 252 from Donn.
  Also: Add SPEF Extractor OpenRCX calibration to installed files
  
• posted: April 8, 2022 at 2:00am     version: 1.0     revision: 308
  Use sky130_ef_sc_hd__decap_12 for fill generation
  Allow EF decap cells to be parallelised
  Also: Updated version to go along with the merge of pull request #212 from Anton Blanchard.
  
• posted: April 7, 2022 at 2:00am     version: 1.0     revision: 307
  Remove Various Deprecated Variables
  Updated version with the merge of pull request #250 from github.
  
• posted: April 6, 2022 at 2:00am     version: 1.0     revision: 306
  Support multiple filter scripts
  filters need filters= prefix
  Also: Fix default_fanout_load
  Also: Correction to the mismatch_params.py script and process_params.py script to avoid missing some statements that put space around the equal sign in "A = B".
  Also: Fix unterminated #ifdef in magic/sky130.tech
  
• posted: April 3, 2022 at 2:00am     version: 1.0     revision: 305
  Made an extension to the handling of "dev/gauss" syntax in the mismatch_params.py script that takes care of a one-off syntax in the sky130_fd_pr__cap_var_hvt model file that has to be handled a little differently than all the others.
  Added a 2nd run of process_params.py (as is done for mismatch_params.py) because the monte carlo process parameters are also split over both the libs.ref and libs.tech directories.
  
• posted: April 1, 2022 at 2:00am     version: 1.0     revision: 304
  Added the PNP device to the includes in "montecarlo.spice". It is not clear if this is sufficient for a monte carlo simulation of the PNP, but at least the device is found by the simulator. There are no monte carlo parameters set in that file for that specific device.
  
• posted: March 25, 2022 at 2:00am     version: 1.0     revision: 303
  Changed the order of the list of buffers to put the largest buffer size first, as recommended by Matt Liberty.
  
• posted: March 23, 2022 at 5:13pm     version: 1.0     revision: 302
  (1) Modified the model filter script to insert an additional line into all.spice for Xyce support. (2) Modified the magic techfile to align the placement of vias and ReRAM layers when an area contains multiple devices (which is probably a bad idea but no reason for magic to screw up the GDS). (3) Corrected the OpenRCX calibration tables (again) after finding that the calculation of fractional fringe shielding was inverted (that error has been fixed in magic).
  
• posted: March 22, 2022 at 2:00am     version: 1.0     revision: 301
  Updated the magic tech file with a complete set of parasitic capacitance coefficients for min/max/nom BEOL corners. Re-ran the OpenRCX calibration using this tech file and added the updated OpenRCX coefficients to the repository.
  Updated VERSION to force a tarball update on the website (no changes to the code base).
  
• posted: March 18, 2022 at 3:00am     version: 1.0     revision: 300
  Added the missing NPN to the all.spice file (correction done in the script "fix_spice_includes.py"). This was mentioned in the script but never implemented.
  Updated the OpenRCX calibration files based on new extraction data from magic using the new modeling of the fringe shielding effect of proximal shapes in magic. Magic's extraction equations before the new implementation would significantly over-estimate the fringe capacitance of closely-spaced wires.
  
• posted: March 17, 2022 at 3:00am     version: 1.0     revision: 299
  Additional changes to the spectre_to_spice.py script in support of onboarding the continuous SPICE models. Also: Added "-j" option to "make timing" for the PDK repository download and update, so that "make timing", which takes a long time, can run a lot faster.
  
• posted: March 15, 2022 at 3:00am     version: 1.0     revision: 298
  Removed the "minenclosedarea" patch for the HD and HDLL libraries and moved the fix to the "fix_techlefA|B.py" scripts. This avoids the use of patch files and avoids having to re-do the patch files to deal with the change in the technology LEF files to cover process corners. Also: made some enhancements to the spectre_to_spice.py script stemming from conversion of the SkyWater continuous models.
  A couple more additions to spectre_to_spice.py, again for the continous model translation.
  
• posted: March 7, 2022 at 4:18pm     version: 1.0     revision: 297
  Expanded the fix_spice_includes.py script to add the missing device cap_var_hvt to the list of includes in all.spice, as pointed out by Stefan Schippers.
  Corrected the Openlane config.tcl file to add the new technology LEF names (nom, min, and max) for the non-ef-format (previously only changed this inside the #ifdef ef_format block).
  Also: Removed the extraneous "rm -f ... rcx_rules.info" line from the Makefile.
  Also: Made a fix to the sky130.json file, which was missing a comma and therefore illegal JSON syntax. Corrected the openlane configuration for the "_OPT" tech LEF from "__max" to "__nom". Made some corrections to the project manager script, which comes up and runs now, although there is plenty of additional work to be done.
  
• posted: March 6, 2022 at 10:34am     version: 1.0     revision: 296
  Modified the sky130 Makefile to prevent the "install" from running concurrently on PDK variants A and B if the "-j" option is passed to "make" to enable a multithreaded build. If concurrent, then files in variant B may install before variant A, preventing the files from being compared and replaced by symbolic links. Note that this does not invalidate anything in the PDK, but it will make the build different from run to run.
  
• posted: March 5, 2022 at 12:00pm     version: 1.0     revision: 295
  Updated the OpenRCX calibration tables with the magic tech and the technology LEF files from the most recent installation of open_pdks.
  
• posted: March 5, 2022 at 3:00am     version: 1.0     revision: 294
  Added a patch file to correct the deep nwell and nwell overlap errors in the original SkyWater layout for the GPIOv2 cell in the sky130_fd_io library.
  
• posted: March 4, 2022 at 3:00am     version: 1.0     revision: 293
  Modifed the technology LEF-fixing script to add in via resistances and fix the one incorrect layer resistance. Created a new script to generate minimum and maximum corner versions of the nominal technology LEF file. Fixed swapped area vs. perimeter capacitances for metal5 in magic. Updated the Makefile and the openlane config script to work with the modified names for the technology LEF and the OpenRCX information files.
  
• posted: March 3, 2022 at 4:55pm     version: 1.0     revision: 292
  Add reram library path to git submodules init
  Simple update to the README to reflect the new ReRAM module in skywater-pdk that will be automatically pulled with "make prerequisites". This merges pull request #227 from Abhinav Uppal on the open_pdks github repository.
  Also: Modified a number of custom scripts (and corresponding calls to the scripts in the sky130 Makefile) to do the following: (1) Revert the change to use the "tempfile" library because this just causes an additional error when the /tmp directory is not in the same filesystem as the staging area (especially as the original method was working fine except for problem #2), and (2) Fix a number of custom scripts to use the correct path to either sky130A or sky130B depending, when needed, on an option passed to the script. Standalone scripts need the option; filter scripts can divine the name of the PDK from the target path.
  
• posted: March 1, 2022 at 3:00am     version: 1.0     revision: 291
  Corrected the Makefile for sky130, which was unsetting PDKPATH to prevent issues with existing environment variables, but also needs to unset PDK_ROOT, or else an existing PDK_ROOT environment variable will override the setting in magic while it is doing the build, and screw up the build.
  Removed the original "rcx_rules.info" file and replaced with six files, three for variant A and three for variant B, comprising minimum, nominal, and maximum process corners.
  
• posted: February 28, 2022 at 3:00am     version: 1.0     revision: 290
  Corrected the sky130.json file, which had a major problem caused by accidentally duplicating a block of text, resulting in an invalid JSON file. Also: Revised the JSON file format so that "commit" is a block rather than a single key-value pair, and is contstructed similarly to the "version" block, with an entry for each tool used in the PDK build (currently magic and open_pdks), to provide a git commit number for each. This has to be done in conjunction with the update of magic to version 8.3.273 to provide the "--commit" command line option.
  Corrected the "defaultoverlap" and "defaultperimeter" entries for metal5 in the magic techfile, which had gotten swapped in yesterday's commit.
  Also: Added a small change to the .magicrc startup file to get rid of any tilde notation in the definition of environment variable PDK_ROOT. This allows files from the PDK to be marked with $PDKPATH in .mag files when the PDK has been installed in a user's local filesystem and PDK_ROOT contains tilde notation.
  
• posted: February 24, 2022 at 3:00am     version: 1.0     revision: 289
  Corrected a problem with scripts overwriting temp files during parallel builds, resolved by using python3's tempfile package. Also: Redid the parasitic capacitance definitions to resolve issues around computing parasitic capacitance to deep nwell structures (mostly), in combination with some changes in magic to automatically handle the short version of the "defaultareacap" and "defaultperimeter" statements in the tech file, to incorporate information about the handling of isolated substrate regions.
  
• posted: February 23, 2022 at 3:00am     version: 1.0     revision: 288
  Corrected the staging_install.py script, where an incorrect conditional was causing symbolic links in sky130B to be made back to the PDK source, NOT the sky130A PDK as it was supposed to be. This change has a major impact on the sky130B PDK installation. Also: Added a missing line in the techfile for magic that declares the parasitic plate capacitance for polysilicon over isolated substrate areas.
  
• posted: February 22, 2022 at 3:00am     version: 1.0     revision: 287
  Updated the capacitance tables in magic to make the precision two values after the decimal place. This may not be necessary but some geometries like long metal5 wires could accumulate errors that might be significant.
  
• posted: February 19, 2022 at 3:00am     version: 1.0     revision: 286
  Added recipes to the Makefiles to execute "make update", which visits all directories in source/ that are git repositories and runs "git pull". Also: Removed the recipe for installing the xschem sky130 library, and added a new one which reflects recent changes in the repository supporting the PDK_ROOT environment variable and supporting the reram device in sky130B. Properly resolved differences in xschem's setup for sky130A vs. sky130B.
  
• posted: February 15, 2022 at 2:34pm     version: 1.0     revision: 285
  Replaced the GDS of the efabless-generated "fill 12" cell for the HD library with a version that is flattened, rather than a cell composed of three other library cells. This should prevent issues with the component cells not being read in at the time that the fill 12 cell is processed. Also: Added sky130B to the .gitignore file in the sky130 directory, so that built PDKs do not try to get themselves into the repository.
  
• posted: February 12, 2022 at 3:00am     version: 1.0     revision: 284
  Updated the magic startup file to use PDK_ROOT instead of PDKPATH.
  Modified the magic device generator script to honor environment variable PDK_ROOT, although the variable does not appear to be used, so it might not make any difference.
  Also: Also corrected the xcircuit startup script to honor environment variable PDK_ROOT, and incremented the open_pdks version.
  Also: Switched from distutils to setuptools.distutils in response to a message from python3 that says that distutils is deprecated and that setuptools should be used instead.
  Also: Corrected the terminal resistance of the "high" and "xhigh" resistors, as the values that were used appeared to be low by a factor of ten (decimal place shift).
  
• posted: February 10, 2022 at 11:41am     version: 1.0     revision: 283
  Modified sky130 Makefile to remove a blockage to parallelism that was preventing the Makefile from building the different PDK vendor libraries in parallel. Also: Made some revisions to the project manager (work in progress). Includes breaking out the python "natural sort" routine into its own file, and not relying on the "natsort" package, which is generally not included with python3 distributions and needs to be pip installed.
  
• posted: February 10, 2022 at 3:00am     version: 1.0     revision: 282
  Added corner extraction styles to the extraction decks in the magic tech file. Currently this affects only layer and contact resistance, as no published information on the high and low metal parasitic capacitance can be found.
  
• posted: February 8, 2022 at 3:00am     version: 1.0     revision: 281
  Revised the IRSIM parameter file header to include the subcircuit device information that was added in the latest commit of IRSIM (9.7.113), which makes IRSIM compatible with .sim file output generated from magic that uses the 'x' notation for subcircuits. Reworked the Makefile to concatenate the header and device parameter files in the irsim/ directory on the fly when building the PDK, and removed the existing concatenated files, which are not needed because they can be regenerated easily.
  
• posted: February 6, 2022 at 5:03pm     version: 1.0     revision: 280
  Modified a number of sky130 custom scripts that were all based on the same code and all generated a file called "temp" during processing, which was causing issues with files getting mixed up when using multithreading (note that the previous commit, which was an attempt to resolve the file mixup error, was a total red herring and had nothing to do with the issue). All of the scripts now append "_temp" to the root name of the original input file being modified, instead of always naming a file "temp". This should resolve the file mixup issue completely.
  
• posted: February 5, 2022 at 4:49pm     version: 1.0     revision: 279
  Moved the main patch file for handling the "nf" parameter position for ngspice compatibility to the filter script that handles the same set of files, since "patch" is failing to work properly with a multithreaded "make" due to creating a common filename "temp" that then gets confused by the threads.
  Updated version to go along with the previous commit.
  
• posted: February 3, 2022 at 3:00am     version: 1.0     revision: 278
  Found one cell still in the sky130_ef_io__gpiov2_pad_wrapped GDS that is also defined elsewhere, and causes the GDS_FILE to change between those two files from run to run, causing indeterminism in the output. Like for the last commit, removed the cell definition and left the cell instance.
  
• posted: February 2, 2022 at 5:32pm     version: 1.0     revision: 277
  Found a potential issue with file locking in magic when working with the I/O pads, which can open enough simultaneous files to exceed the file descriptor limit on some OS variants. Also: Reduced the "gpiov2_pad_wrapped" file to only contain the SkyWater cells by reference, and not redefine them, which is both unnecessary and puts a large GDS file into the repository.
  
• posted: February 2, 2022 at 9:26am     version: 1.0     revision: 276
  Added natural sort after glob.glob in two places in foundry_install.py because the sort order when listing cells for generating magic databases can alter the output.
  
• posted: February 2, 2022 at 3:00am     version: 1.0     revision: 275
  sky130: skip xschem files copy when disabled
  Updated version to go along with the merge of pull request #215 from Johan Euphrosine (fixed disable option for xschem in the Makefile---the same method needs to be applied to all of the options that can be disabled, per issue #177).
  
• posted: January 27, 2022 at 3:00am     version: 1.0     revision: 274
  Added a new simple script that allows additional geometry to be spliced into a magic database file, and wrote a custom exception into the Makefile that merges two pwell regions in one of the HD library cells, which works around an extraction issue in magic. Eventually the issue will be resolved in magic the correct way, and the custom exception can be removed.
  
• posted: January 25, 2022 at 3:00am     version: 1.0     revision: 273
  Modified the .lib and .lef library file generator scripts so that they follow glob.glob() with natural_sort() (taken from the sort_pdkfiles.py script). Probably the real solution here is to not remove filelist.txt as early as it is removed in foundry_install.py. As written, the file no longer exists when certain libraries are generated as a result of being created from scratch by magic instead of just collected and compiled from vendor sources. Probably the list of cell names in filelist.txt is still valid at that point.
  Added natural sorting to the remainder of the library generation scripts, as it's obvious that any kind of sorting is preferable to the randomized ordering caused by using glob.glob().
  
• posted: January 23, 2022 at 3:00am     version: 1.0     revision: 272
  Made several improvements for handling timestamps. All of the .mag files generated now get a timestamp that is derived from the date of the last open_pdks commit. In particular, the abstract and full views of cells both have the same timestamp, so changing views by dereferencing won't result in timestamp updates. This is not as good as implementing a checksum method, but it is an improvement over having all timestamps being the time at which each individual file was written.
  
• posted: January 21, 2022 at 3:00am     version: 1.0     revision: 271
  Made a correction to the magic sky130 techfile to correct the use of "licont" in the cifinput section. This should have been "barelicont". It makes a difference when reading GDS from tools other than magic where CONT and LI are together in a cell without any other layers to resolve which kind of drawn contact is represented in magic.
  One final correction to the last commit (forgot to change the templayer name from gencont to barelicont). Also, found that the compose rules put in recently for dealing with coreli were missing the mid-voltage diffusion layers mvpsd, mvnsd, mvpsc, and mvnsc, so these were added. Otherwise, SONOS cells with the required COREID layer have problems reading in, as the coreli layer ends up overdrawing substrate and well contacts and erasing them.
  
• posted: January 20, 2022 at 3:00am     version: 1.0     revision: 270
  new release to mr deck + non-mr deck
  Updated version to go along with the merge of pull request #207 from Marwan Abbas (new and modified klayout DRC decks).
  Also: Added "--with-sky130-variants=" to the configuration, so that the compile and install can be restricted to only sky130A or sky130B. The default is to compile and install both variants, equivalent to "--with-sky130-variants=all".
  Also: Updated the sky130 README file to include the new --with-sky130-variants configuration option.
  Also: Corrected a pair of custom mask hints added to the sky130_fd_sc_hd cell to prevent issues with writing hierarchical GDS. The areas in the hint were rounded off, leading to the addition of slivers of PSDM added over the tap cell on output and potentially causing DRC spacing errors to neighboring cells.
  
• posted: January 19, 2022 at 3:00am     version: 1.0     revision: 269
  Finished first draft of ReRAM support for Sky130. This completes the modifications started with yesterday's commit, which split the ReRAM-enabled process to PDK name sky130B. Today's commit handles the differences between PDK variants A and B, which are namely (1) The technology LEF files (parasitic capacitance values for metals from metal2 and up changed), and (2) The magic tech file (parasitic capacitance values changed, and layer heights changed).
  Modified the rule for generating COREID so that it is not generated automatically by the SONOS layer. This is in conflict with the SkyWater rule, but the SkyWater rule pertains to a specific NV RAM core cell that is not part of the open PDK, and it is not a manufacturing rule error. Removing COREID from around SONOS solves more problems than it creates.
  
• posted: January 18, 2022 at 3:00am     version: 1.0     revision: 268
  Worked out a way to make the sky130 Makefile (mostly) variant- independent, so that new process variants can be added without having to duplicate all of the different Makefile recipes for each new variant. This commit removes the ReRAM support from sky130A, which was intended to be temporary. By end-of-day today, the ReRAM support should be back, in new variant sky130B.
  Some corrections to the Makefile, and a change to sky130.json to list the ReRAM in the set of options in sky130B/.config/nodeinfo.json.
  
• posted: January 14, 2022 at 3:00am     version: 1.0     revision: 267
  Corrected two I/O cells, one custom, one original, both of which were already custom GDS files in open_pdks, and both of which contained violations of nwell overlapping dnwell edge on the inside.
  
• posted: January 12, 2022 at 3:00am     version: 1.0     revision: 266
  Added a rule to the magic DRC deck to check for low-voltage diffusion inside a high-voltage nwell.
  Created a custom script to add the line "USEMINSPACING OBS OFF" to each of the standard cell technology LEF files. This is the correct setting, as otherwise macros with obstruction areas won't be handled correctly by place & route tools. Also: The custom script causes the technology LEF file to flag as a mismatch in the "patch" file, and "patch" creates a backup file with a ".orig" extension. So the ".orig" extension has been added to the list of file extensions to ignore when doing "make install".
  Also: Added missing nsd.1, nsd.2, psd.1, and psd.2 rules to the MR rule deck in klayout.
  
• posted: January 5, 2022 at 2:07pm     version: 1.0     revision: 264
  Corrected an error in the ReRAM additions to the magic technology file that inadvertently specified that via1 cannot overlap in overlapping cells. The rule was supposed to be that via1 cannot overlap ReRAM. This has been corrected.
  
• posted: January 5, 2022 at 3:00am     version: 1.0     revision: 263
  Modified the staging_install.py script to do something that it claims to do but wasn't, which is to remove all the ".magicrc" files that were created in the staging area but which don't belong in the destination because they are temporary files. This fixes issue #204 on the github issue tracker for open_pdks.
  
• posted: January 2, 2022 at 3:00am     version: 1.0     revision: 262
  Several corrections: (1) Netgen setup for sky130 changed to split out the ESD nFET and pFET to give them a 7% tolerance in width instead of the usual 1% tolerance, because magic calculates the effective width due to the flanged gate slightly differently. (2) Corrected the parameterized devices in magic, which had wrong routine names for the inductor devices, and an incorrect spelling for two of the vertical parallel plate capacitors. (3) Added length and width to the short/open resistors in sky130_fd_io.spice. (4) Corrected a connection to the OGC_HVC pin in the verilog for the power pads (the pin is floating, so the connection is not important, but needed for LVS). Items (3) and (4) are incomplete and ongoing.
  
• posted: January 1, 2022 at 3:01am     version: 1.0     revision: 261
  Updated and corrected some of the parasitic extraction tables in the magic techfile for sky130 (again). This corrects issues around the use of the "isosub" layer in conjunction with the update in magic version 8.3.248, defining "isosub" and "dnwell" as shield types to substrate, and defining equivalent parasitic capacitances between all layers and "isosub" or "dnwell".
  Trying to knock down all of the unknown layer/purpose pairs that are unused in magic but found in SkyWater GDS files and so generate error messages on GDS read-in.
  Also: Corrected one of the entries just added for ignoring unused layer: purpose pairs in magic.
  Also: Added 81:20 (pad center ID) to the list of ignored layer:purpose pairs in the magic tech file.
  Also: Added the ESD 5V nFET and pFET to the list of devices recognized as FETs by the netgen setup.
  
• posted: December 31, 2021 at 3:00am     version: 1.0     revision: 260
  Added some CDL-isms to the list of properties to ignore in the netgen setup file for sky130A. It would be better to remove these CDL-isms from the custom file spice/sky130_fd_io.spice, but that is a complicated task that will have to wait for another day.
  Corrected the parasitic capacitance tables in the magic techfile to account for deep nwell to substrate, and shielding of fringing capacitance from poly and all metal layers to substrate by nwell and pwell, which was missing. The missing shielding caused nodes to have coupling capacitance to substrate even when they were shielded from substrate (the plate area capacitance was calculated correctly, but the fringing capacitance can be large).
  Also: Found some other entries in the parasitic capacitance tables in the magic tech file, and corrected them.
  
• posted: December 30, 2021 at 3:00am     version: 1.0     revision: 259
  Changes for sky130_sram macros.
  Updated version to go along with merge of pull request #205 from Mitch Bailey (fixes the SPICE netlists for the SRAM macros).
  Also: Modified the sp_to_spice.py script so that it removes the filename with the original extension after filtering.
  
• posted: December 29, 2021 at 3:00am     version: 1.0     revision: 258
  Added a custom file to correct the error in the sky130_fd_sc_hvl__lsbufhv2lv_1.spice file in the skywater-pdk library. The error is that the two independent power rails, which have the same port name in the SPICE netlist, were split into two nets, and one of the nets was not declared as a port, making the cell invalid. The fix gives the two independent nets the same name, which is also invalid, and not ideal, but it is consistent with the other files (LEF, verilog, etc.) and the error resolves itself at the next level of hierarchy when running LVS, so it is usable that way.
  
• posted: December 24, 2021 at 3:00am     version: 1.0     revision: 257
  Additional corrections to the new ReRAM layers in the magic tech files. Also corrected the GDS-exact tech file to avoid having text or pin purpose metals erase vias when they overdraw them.
  Corrected the off-grid shapes in the sky130_fd_sc_hd__a2111o_1.gds file and generated a custom GDS file for the cell. Note that these shapes are on non-mask layers (pin text) and so do not represent a manufacturing error, but they do raise an error when read into a layout editor like magic.
  
• posted: December 22, 2021 at 3:00am     version: 1.0     revision: 256
  Fix typo in configure command line option documentation
  Remove old configure command line options from documentation
  Also: Made additional changes to the README file, especially to note the use of DESTDIR and SHARED_PDKS_PATH passed to the Makefile, as that is what replaces the deprecated "--with-local-path=" and "--with-dist-path=" in the configuration.
  Also: Fixed the preproc.py script to be able to handle non-ASCII data, as some files like the klayout files are using UTF-8 encoding, and the last update to a klayout file broke the open_pdks install. For now, this is an option to the preprocessor script ('-utf'), but it could and probably should just be the default setting. Likewise modified the staging install script so that substitutions can be made on files containing the occasional non-ASCII characters. Also in this update: Corrections to the handling of RERAM in the magic techfile.
  
• posted: December 17, 2021 at 3:00am     version: 1.0     revision: 255
  update Klayout MR DRC deck
  Move some layer info from OpenLane
  Also: Updated version to go along with the merge of pull requests #199 and #200 on github.
  Also: Updated the Makefile.in from a patch file provided by Stefan Schippers corresponding to fixes for, and updates to, xschem.
  
• posted: December 16, 2021 at 3:57pm     version: 1.0     revision: 254
  Corrected the custom decap 12 cell. . . again (was missing a shape on local interconnect).
  
• posted: December 16, 2021 at 12:38pm     version: 1.0     revision: 253
  Corrected an issue with the custom decap_12 cell with pared-down local interconnect, which had the original name sky130_fd_sc_hd__decap_12 in the GDS file as the cell name, causing the cell to get replaced in the library with some version derived from the abstract view (not quite sure how open_pdks does that, but the problem is in the GDS, not in open_pdks).
  
• posted: December 8, 2021 at 3:00am     version: 1.0     revision: 252
  Added a script that specifies the port USE and DIRECTION for pins VPB and VNB for all digital standard cell libraries (other than hvl), since the original LEF files used to annotate the GDS don't have those pins. This is supposed to resolve issues with OpenROAD tools crashing when dealing with these LEF files.
  Corrected nearly all of the filter files, which will throw an exception instead of a graceful error message if the input file is not found. The problem that exposed this error, though, was a simple misplaced line in the sky130 Makefile, which has been corrected.
  
• posted: December 3, 2021 at 3:00am     version: 1.0     revision: 251
  Added liberty files for a number of the I/O pad cells, mainly to cover the set used on the caravel chip design, including the sky130_ef_io set. This supports the new capability of Openlane to do top-level timing analysis.
  
• posted: December 1, 2021 at 3:00am     version: 1.0     revision: 250
  Made two changes to foundry_install.py: (1) Adds the line "gds drccheck false" before generating .mag files. Without this line, .mag files created from GDS get "checkpaint" entries that force magic to run DRC checks whenever the cell is loaded, which in turn updates all the timestamps and makes magic want to write out every cell as updated. This should no longer happen. (2) Added a "dorcx" option to "-gds" for foundry_install.py. Only if this is specified will generated SPICE output contain parasitics. Otherwise, SPICE cannot be generated for LVS (can only get SPICE netlists for LVS if they are copied from source, not generated by extraction).
  
• posted: November 30, 2021 at 3:00am     version: 1.0     revision: 249
  Use much faster gzip compression.
  Try bzip2 otherwise github runs out of disk space.
  Also: Output disk space usage.
  Also: Remove files to prevent running out of disk space.
  Also: More aggressive removal.
  Also: Updated version to go along with the merge of pull request #196 by Tim Ansell.
  
• posted: November 28, 2021 at 3:00am     version: 1.0     revision: 248
  added the updated DRC deck, LVS script, modified the options in tech file for def import
  Delete lvs_sky130.lylvs
  Also: removed gen_run_drc.py not needed anymore
  Also: changed deck version for the most stable version
  Also: Updated version to go along with the merge of pull request #194 from Maran Abbas.
  
• posted: November 27, 2021 at 3:00am     version: 1.0     revision: 247
  Revised the top-level Makefile so that it does not need to declare targets for each technology but will enumerate the valid technologies discovered at the time of doing "autoconf" and the enabled technologies declared by "configure". Also modified the "find" command in the configure script to search symbolic links. This allows additional target technologies to be added to the directory without needing to update the top-level Makefile (although "autoconf" will have to be re-run), and it allows new technologies to be added by symbolically linking to the directory. This is important for non-free technologies that cannot be distributed with open_pdks.
  Corrected Makefile.in to build only PDKs enabled by "configure".
  Also: Added generation of OPENPDKS_TOP from the configure script to support technologies added as symbolic links, which can't use ".." to get back to the package top to reach the script files.
  Also: Modified foundry_install.py so that other scripts in the common/ directory can be found even if foundry_install.py is called from a directory following a symbolic link.
  Also: Corrected the comments in foundry_install.py regarding the use of option "up", which was changed at some point to have the syntax "up=", but which was not changed in the instructions.
  Also: Modified cdl2spi.py so that a $[model] directive on a bipolar transistor generates a warning but not an error.
  
• posted: November 25, 2021 at 1:48pm     version: 1.0     revision: 246
  Improve the sub-tool calling.
  Include input script in error message.
  Also: Updated version to go along with the merge of pull request #189 from Tim Ansell.
  
• posted: November 25, 2021 at 11:26am     version: 1.0     revision: 245
  Use `pipefail` so make sees command failures.
  ci: Capture the created PDK as output.
  Also: ci: Capture more output.
  Also: ci: Check for the PDK output inside the tar command.
  Also: ci: Specify the find directory.
  Also: ci: Prevent expansion of prune pattern.
  Also: ci: Output captured files (and always succeed).
  Also: ci: Nicer capture output on tar creation.
  Also: Updated VERSION to go along with the merge of pull requests #186 and #192 from Tim Ansell.
  
• posted: November 25, 2021 at 3:00am     version: 1.0     revision: 244
  Preliminary support in Magic for ReRAM. Putting this support in sky130A is a temporary solution, as the ReRAM metal stackup is different (mainly with respect to parasitics) and requires that there be a new variant sky130B supporting ReRAM and the altered stackup. The temporary solution will allow people to design ReRAM based projects while we revise parasitics for the stackup.
  Updated version.
  Also: Modified the name of the ReRAM subcircuit model to match the change made to google/skywater-pdk-libs-sky130_fd_pr_reram on github.
  
• posted: November 20, 2021 at 3:00am     version: 1.0     revision: 243
  Corrected the Makefile recipe for the sky130 SRAM macro library to change the installed SPICE file from the ".lvs.sp" to the ".sp" one, as the former uses SI units and is not compatible with the sky130 PDK.
  
• posted: November 19, 2021 at 3:00am     version: 1.0     revision: 242
  Added a few DRC rules to the magic tech file that allow poly to cross p-tap in a memory core cell, creating a parasitic p-varactor.
  
• posted: November 18, 2021 at 3:00am     version: 1.0     revision: 241
  Corrected the layout, GDS, and LEF views of the "clamped3" pads, which were missing the "VCCHIB" port.
  Implemented the photodiode device in the parameterized device generator for magic.
  Also: Corrected a rule that prevented the npass FET from getting as close to a SONOS FET as it is allowed, which is 0.21um (poly-to-poly spacing rule).
  Also: Added rule for diffusion contact to SONOS gate (0.075um).
  
• posted: November 16, 2021 at 3:00am     version: 1.0     revision: 240
  Rework naming in `staging_install.py` to clearer.
  Adding verbose flag to output more information.
  Also: Revised staging_install.py slightly to retain the original options "target" and "local" as alternatives for "writeto" and "finalpath", respectively. This retains backwards compatibility with a minimum of effor. Also: Updated VERSION to go along with the merge of pull request #175 from Tim Ansell.
  Also: Convert travis CI to GitHub Actions.
  Also: Fix the magic build.
  Also: Corrected the sky130_ef_sc_hd__decap_12.gds file, which had incorrect label layers, causing issues with LVS when read into magic, even though the mask layout was valid.
  Also: Replaced an accidentally-deleted line from the sky130 Makefile that prevents the base I/O verilog macros from being included into the I/O verilog library.
  Also: Corrected an error in the new sky130_ef_io__vccd_lvc_clamped3_pad layout that internally shorts pad power to VSSD ground.
  
• posted: November 14, 2021 at 3:00am     version: 1.0     revision: 239
  Replace SYNTH_DRIVING_CELL with size 2 inverters
  Updated version to go along with the merge of pull request #172 from Donn.
  
• posted: November 12, 2021 at 5:02pm     version: 1.0     revision: 238
  Added new pad types for use in the caravel and caravan chips for the user 1.8V voltage domains; these pads have clamp connections but do not connect to the pad ring, and rely on the power supply being routed inside the chip core.
  Updated foundry_install to change the recent "hide" option addition to a more general-purpose "lefopts" for passing "lef write" options to magic. With this, and with an update of magic, new LEF views of all standard cells are now generated that are all consistent and do not depend on the SkyWater LEF sources except for annotation. LEF views of selected I/O cells were edited to remove DRC errors and for the bus filler cells, to remove the obstruction layer from the area typically used to drop additional cells into the padframe.
  
• posted: November 9, 2021 at 3:00am     version: 1.0     revision: 237
  Allow SHARED_PDKS_PATH to be set externally.
  Updated version to go along with the merge of pull request #171 from Matt Guthaus.
  
• posted: November 6, 2021 at 3:00am     version: 1.0     revision: 236
  Added a filter script that inserts a liberty file format snippet containing wire models into each standard cell library liberty timing file. Note that the wire load model may not be appropriate for all corners or all libraries, but may be used as a stand-in and adjusted as necessary if more specific wire load models are developed.
  Added "no-copy" and "include" functions to the existing "exclude" to handle the process of replacing existing vendor cell views with custom cell views. Added a syntax to all three functions that is / and allows names for groups of cells to be taken from a location other than the source; e.g., from a custom directory where replacements are found. Updated the Makefile for sky130 to make use of the standard cell replacements (in particular, corrections to GDS layout), and to better integrate additions to the libraries.
  Also: Updated version to go along with the last commit.
  
• posted: October 29, 2021 at 3:00am     version: 1.0     revision: 235
  Corrected an offset in the sky130_ef_io__vdda_hvc_pad layout and also regenerated the sky130_ef_io.gds (which had the incorrect pad just mentioned).
  Updated version with the last commit correcting a pad in sky130_ef_io.
  
• posted: October 25, 2021 at 1:23pm     version: 1.0     revision: 234
  Remove buf_1 from the cts buffer list
  Updated version to go along with the merge of pull request #169 from Manar Abdelatty.
  
• posted: October 23, 2021 at 3:00am     version: 1.0     revision: 233
  Corrected an error in the sky130 Makefile, which had not been updated to reflect the fact that the file openlane/common_pdn.tcl had been removed.
  
• posted: October 22, 2021 at 3:00am     version: 1.0     revision: 232
  Remove common_pdn.tcl
  Updated version to go along with the merge of pull request #167 from Manar Abdelatty.
  
• posted: October 15, 2021 at 3:00am     version: 1.0     revision: 231
  Update synth drving cell and cap load for all std cell variants
  Updated version to go along with the merge of pull request #166 from Manar Abdelatty.
  
• posted: October 14, 2021 at 3:00am     version: 1.0     revision: 230
  Added a patch for the "wire 1" syntax error in the sky130_fd_sc_hd library verilog. This error shows up when a specific flop type is used in a gate-level verilog simulation.
  
• posted: October 6, 2021 at 3:00am     version: 1.0     revision: 229
  Parameterize PDK specific variables in common_pdn.tcl
  Updated the version to go along with the merge of pull request
  
• posted: October 5, 2021 at 3:00am     version: 1.0     revision: 228
  Add default_max_tran
  Updated version to go along with the merge of pull request #164 from Manar Abdelatty.
  Also: Added Harald Pretl's Python script that can convert the sky130.lib.spice file to extract a single corner and output a valid library file with only the one corner; this greatly speeds up ngspice, which does not handle the library file parsing gracefully. Thanks to Harald for the contribution!
  
• posted: September 22, 2021 at 3:00am     version: 1.0     revision: 227
  Change to yesterday's commit to move the specify section from the strength-specific cell to the base cell, since the signal names in the specify section match those in the base cell.
  
• posted: September 21, 2021 at 3:00am     version: 1.0     revision: 226
  Added some (disabled) code to the inc_verilog.py script which inserts the "specify ... endspecify" block into each of the standard cells in the verilog library.
  
• posted: September 17, 2021 at 3:00am     version: 1.0     revision: 225
  Update common_pdn.tcl
  Updated version to go along with the merge of pull request #161 from Manar Abdelatty.
  
• posted: September 16, 2021 at 3:00am     version: 1.0     revision: 224
  Updated the magic techfile to have the correct value for the p-substrate (4400 ohms/square), and to include "isosub" in the same resistance list.
  
• posted: September 15, 2021 at 11:30am     version: 1.0     revision: 223
  Corrected the sky130.lib.spice (again) to remove the redundant includes of "all.spice", the base corner model file, and the non-FET corner model file, all of which are included by the top-level corner model file.
  
• posted: September 15, 2021 at 3:00am     version: 1.0     revision: 222
  Add DATA_WIRE_RC_LAYER, CLOCK_WIRE_RC_LAYER to config
  Corrected the qflow setup scripts so that the voltage range string in the liberty file name is a variable that can be processed by the preproc.py script, so that the string can be properly specified for the HVL library. Also: Removed a wayward $ from one of the makefile recipe entries, which was causing a qflow file to be saved with the wrong filename.
  Also: Removed the "sky130_osu_sc" library as a configure target, since it is not really a library but is used to create the t12, t15, and t18 libraries, which are already targets. Attempted to clean up some of the mess with the OSU libraries and files being variously called, e.g., "18t", "t18", and "18T". This has not been completely resolved yet.
  Also: Corrected sky130.json to remove the base OSU library, which is not used.
  Also: Removed the various scripts and edits around the sky130.lib.spice file and just included a complete sky130.lib.spice file to replace the original wholesale. This includes a simplication to include a corner file, e.g., corners/tt.spice, instead of including the contents of that file individually; especially since the individual list was missing the 20V nFET and pFET devices.
  Also: Reverted the temporary change to the wafflefill algorithm, which had very little effect in practice.
  
• posted: September 13, 2021 at 3:00am     version: 1.0     revision: 221
  Corrected the addition to Makefile.in from a recent commit, as the target argument to preproc.py must be a file, not a directory (although accepting a directory argument a la the "cp" command seems like a reasonable behavior to add).
  
• posted: September 10, 2021 at 3:00am     version: 1.0     revision: 220
  Modified the xcircuit files to set PDK_ROOT as a local variable and to use that variable in the library .lps files to make them more portable. Modified the staging_install script to make substitutions on the parent path (equivalent to PDK_ROOT) as well as the source path (equivalent to PDK_PATH).
  Corrected the Makefile target for nodeinfo.json which had typos in the digital standard cell paths.
  
• posted: September 9, 2021 at 3:00am     version: 1.0     revision: 219
  The fix to add "-S" to "env" to allow the "-B" switch to be passed to python apparently doesn't work in CentOS, so both switches have been removed. Moved the cdl2spi.py script back to common/ because it is used by scripts in both common/ and runtime/; an additional line in the top-level Makefile is then needed to install cdl2spi.py.
  Added code to foundry_install.py to catch and report a couple of errors that can otherwise cause the script to fail and exit.
  Also: Additional correction; the sky130/Makefile.in missed passing the "-ef_format" option parameter to scripts that were run outside of foundry_install.py.
  Also: Corrected the Makefile.in, which was not correctly identifying the presence or absence of paths to various optional library sources, and so was attempting to install all optional libraries whether or not they existed. This would result in an error but was apparently otherwise harmless, but now the build output is now cleaner.
  Also: Separated out the different libraries into individual Makefile recipes. This avoids creating directories and throwing errors when attempting to build a library submodule that has not been initialized in the skywater-pdk repository. Also added a missing install line for custom GDS files in the HS and HVL digital libraries.
  Also: Corrected comment lines that had been incorrectly inserted inside a monolithic "if" block without backslashes (moved the comment lines outside of the block).
  Also: Changed the sky130/Makefile so that libraries in skywater-pdk that did not get "submodule init" run on them will appear with commit ID "unknown" in the nodeinfo.json file.
  Also: Corrected the xcircuit library for sky130_fd_sc_hd so that the library path is correct for ef-format.
  
• posted: September 6, 2021 at 11:24am     version: 1.0     revision: 218
  Update to PDN Config
  Updated version to go along with the merge of pull request #158 from Donn.
  
• posted: September 2, 2021 at 3:00am     version: 1.0     revision: 217
  Modified makefile to install runtime files using a for loop, made sure files were referring to PREFIX correctly
  Updated version to go along with the merge of pull request 157 from Max Chen.
  
• posted: August 31, 2021 at 8:01pm     version: 1.0     revision: 216
  Copy the rcx_rules file
  Updated version to go along with the merge of pull request number 155 from Manar Abdelatty.
  Also: Added a line to fix_device_models.py to remove the 3rd terminal from the calls to sky130_fd_pr__res_generic_po in the "conb" gates in the digital standard cell libraries.
  Also: Implemented the change in pull request #156 (not doing a pull request merge because the mirror database is behind the one on opencircuitdesign.com).
  Also: Modified the way filter scripts are called so that they will always get the option argument "-ef_format" if EF_STYLE is set. This fixes the method used in a recent commit which was supposed to do the same thing but didn't.
  
• posted: August 31, 2021 at 3:00am     version: 1.0     revision: 215
  Fixed shebang line in some python scripts, added .txt files, and scripts/configure now installs natsort
  moved scripts from 'common' folder to 'runtime;' modified top-level makefile to install scripts in 'pdk/scripts' instead of 'pdk/bin'
  Also: Moved install files from runtime back to common; modified makefile to reflect changes
  Also: Moved common-related files back to common and updated Makefile.in
  Also: Corrected sort_pdkfiles.py path
  Also: Removed "requirements.txt" from the runtime directory, as that is related to the virtual environment used at efabless and not relevant here. Corrected the handling of $prefix in the top level Makefile, so that installation of the run-time scripts is now correct.
  
• posted: August 28, 2021 at 3:00am     version: 1.0     revision: 214
  Added a script to modify the "all.spice" file and add the missing 3.4um x 3.4um emitter PNP device.
  Fix space
  Also: Updated version to go along with merge of pull request 152 from Manar Abdelatty, and other changes made today.
  Also: Revised several custom sky130 scripts to accept the option "-ef_format" and handle the syntax of the filesystem under libs.ref/ accordingly. Change only affects installations using EF_STYLE=1.
  
• posted: August 27, 2021 at 3:00am     version: 1.0     revision: 213
  Added processing to the SRAM core device model files to remove parameters that are both unnecessary/unused and incompatible with Xyce.
  
• posted: August 26, 2021 at 3:00am     version: 1.0     revision: 212
  Path bug fix preventing the qflow manager from displaying the proper technology files
  Updated qflow recipe to use original cell names
  Also: Updated version to go along with the merge of pull request #150 from Max Chen.
  
• posted: August 24, 2021 at 9:08am     version: 1.0     revision: 211
  Failed to check in the change to the Makefile yesterday.
  
• posted: August 24, 2021 at 3:00am     version: 1.0     revision: 210
  Forgot to run autoconf after the last change to the configure.ac script to change the default location from /usr (forced behavior) to the standard /usr/local (default behavior).
  
• posted: August 22, 2021 at 3:00am     version: 1.0     revision: 209
  Changed qflow install recipe so setup file names match pdk node names.
  Updated VERSION to go along with the merge of pull request #149 by Max Chen.
  
• posted: August 21, 2021 at 3:00am     version: 1.0     revision: 208
  Added select flow dialog
  removed test functions, cleaned up code
  Also: Updated VERSION to go along with the merge of pull request #148 from Max Chen.
  Also: Remove trailing whitespace from files.
  Also: Strip trailing whitespace in README file.
  Also: Rename README to docs.txt
  Also: Update the documentation for ./configure usage.
  Also: Fix the travisCI scripts.
  Also: Put build in the staging path name to make logs clearer.
  Also: Resolved merge conflict of sky130/Makefile.in
  Also: Add missing license header.
  Also: Minor cleanup after merging pull request #127 from Tim Ansell.
  Also: Removed the default prefix of /usr, which makes the default prefix /usr/local. This breaks backwards compatibility with various documentation, videos, etc., but conforms with standard Linux practices, however misguided they may be. Once the open_pdks Sky130 distribution becomes a package (which is inevitable, given how long the installation takes), then the documented /usr/share/ will be correct anyway.
  Also: Corrected the top-level Makefile to add "/share" after the prefix, so that the open_pdks scripts go in ${prefix}/share/pdk/bin/ as they are expected to, while the SkyWater PDK goes in ${prefix}/share/pdk/sky130A/. Changed the instructions in docs.txt so that the distributed install works as advertized (swapped the definitions suggested for prefix and DESTDIR).
  Also: Removed the extraneous and unnecessary "build" directory from the staging path.
  Also: Corrected top-level Makefile to use $datadir instead of $prefix for constructing the install target for common scripts and such.
  
• posted: August 20, 2021 at 3:00am     version: 1.0     revision: 207
  Add openrcx rules file and the related environment configs for openrcx support in openlane
  Add Layer RC values
  Also: Remove space
  Also: Set klayout dbu to 0.001
  Also: Updated the VERSION file to go along with the merge of pull requests 145 and 146 from Manar Abdelatty.
  Also: Modified the "wafflefill" cifoutput style to deal with the problem of certain positional offsets preventing FOM fill in otherwise fillable areas; this causes poly fill to fill those areas so that the areas become too low density in diffusion. The solution is to add an in-between pass that uses the same size fill shapes as the FOM first pass, but with a Y offset of half the FOM fill row pitch. The proper solution is to have a progressive Y offset like the progressive X offset, but that needs to be coded in magic.
  Also: Added a missing DRC rule to check diffusion spacing between LV diffusion and MV diffusion.
  
• posted: August 15, 2021 at 3:00am     version: 1.0     revision: 206
  Added GDS file for custom alternative to the fill 8 cell in the HVL library, with diffusion layers to raise the percentage of FOM fill.
  Removed IP and Import windows from project manager screen. Added an import button that brings up a file explorer for users to import subprojects or projects with a symbolic link. Small treeview UI changes.
  Also: Added more features to the import dialog and treeview now displays all subprojects recursively
  Also: Treeview can now highlight last opened subprojects
  Also: Updated VERSION to go along with the merge of pull request 144 from Max Chen.
  
• posted: August 9, 2021 at 3:00am     version: 1.0     revision: 205
  Project manager displays subprojects (projects located under the 'subcells' folder) in the project treeview. Changed some of the buttons on the project manager home screen.
  Deleted line breaks
  Also: Users can create subprojects using the 'New' button
  Also: Modified VERSION to go along with the merge of pull request #142 from Max Chen.
  
• posted: August 6, 2021 at 3:00am     version: 1.0     revision: 204
  Replaced project.json with info.yaml in places asking for basic project info. Renamed some variables that still referred to 'og.' Added create_yaml() method.
  Correct environment path in foundry_nodes.py and removed 'Open Galaxy' from comments.
  Also: Updated VERSION with the merge of pull request #141 from Max Chen.
  Also: Corrected several rules in the magic techfile: (1) The "Tap not contacted" error did not consider that varactor diffusion is continuous across the whole varactor, so that the varactor gate area should be considered as part of the tap area for this rule. (2) The N-diffusion to P-tap distance (latchup rule) should not include the varactor as part of the diffusion checked for this rule.
  
• posted: August 5, 2021 at 3:00am     version: 1.0     revision: 203
  Modified og_gui_manager.py to make it accessible on devices not on the efabless platform. Changed the create project script to make the proper config directories so that the editors can be used. Modified profile.py to make the settings properly reflect the user preferences.
  Replaced top environment line of files with env
  Also: reverted sky130/makefile.in, renamed files starting with 'og,' replaced hard-coded path in create_project with PREFIX
  Also: Updated VERSION with merge of pull request #139 from Max Chen.
  
• posted: August 3, 2021 at 3:00am     version: 1.0     revision: 202
  Update OL config.tcl
  Updated VERSION with merge of pull request #140 from Manar Abdelaty.
  
• posted: July 30, 2021 at 3:00am     version: 1.0     revision: 201
  Added a custom fill_4 cell for the HD library, equivalent to what was done in a previous commit for fill_8, to add diffusion into the cell that can be used for solving FOM density issues.
  
• posted: July 29, 2021 at 3:00am     version: 1.0     revision: 200
  Added correction for the layout of sky130_fd_sc_hs__decap_8. Like the other GDS corrections for the HD library, these have not been folded into the PDK installation, because the install script does not support that procedure yet.
  
• posted: July 27, 2021 at 3:00am     version: 1.0     revision: 199
  Corrected the sky130.json file syntax (simple string arguments had been changed to dictionary arguments without the delimiters being changed from brackets to braces). Thanks to Max Chen for the fixes.
  
• posted: July 24, 2021 at 3:00am     version: 1.0     revision: 198
  Added "resist ... None" entries in the extract section of the magic techfile to ensure that "comment" and other similar layer types are not extracted as nodes in the extraction output.
  
• posted: July 23, 2021 at 3:00am     version: 1.0     revision: 197
  Added a mask-hints line for HVNTM, since certain layout geometries need to have this layer manually created, or else the auto-generated layer can be all over the place and violating numerous rules.
  Corrected the LICON rules in the klayout DRC decks, because the special non-square LICONs used for the high-value poly resistors only applies to resistors having the RPM layer.
  
• posted: July 22, 2021 at 3:00am     version: 1.0     revision: 196
  Modified the techfile to make the cifoutput style "sky130(vendor)" the default, since the prior default "sky130()" does not appear to be necessary or useful. Added an alternative fill size 8 cell with diffusion on top and bottom which acts as FOM fill.
  
• posted: July 20, 2021 at 3:00am     version: 1.0     revision: 195
  Updated version after mergins pull request 138 from Max Chen.
  Update to the Makefile.in from Max Chen to correct an issue with the previous commit. xschem test files now all include the correct library from the top.
  Also: Modified the "fake diode" layout to include a square of unconnected pdiff on the top side, which helps to prevent issues with FOM density.
  
• posted: July 16, 2021 at 3:00am     version: 1.0     revision: 194
  Added the "MR" (manufacturing rules) DRC deck for klayout.
  
• posted: July 14, 2021 at 3:00am     version: 1.0     revision: 193
  Made a change to the xschem install to modify the links to the SkyWater libraries at the bottom to point to the location in the open_pdks install.
  
• posted: July 13, 2021 at 3:00am     version: 1.0     revision: 192
  Updated sky130_ef_io_core.lef and sky130_fd_io_core.lef to match the new caravel
  Updated version to go with merge of pull request #137 from Marwan Abbas.
  Also: Added a new script that can print the creation and modification dates of the library header of any GDS file. Modified the "fakediode_2" cell to put back the diffusion layer---this version only removes the contacts from the original diode cell. This prevents issues with FOM fill generation when using the fakediode cell.
  
• posted: July 8, 2021 at 3:00am     version: 1.0     revision: 191
  Re-instituted a block of code that was deleted from the inc_verilog.py script in sky130/custom/scripts/. The problem was an incorrectly formatted diagnostic output making it appear that the block of code was doing nothing. In fact, the block of code is critically important for the installation of the sky130_fd_io library. The block has been put back in, and the diagnostic print statement now produces the correct output.
  Added the "isosub" to the cifinput and cifoutput sections, mapping it to the "substrate cut" (GDS 81:53) layer. This allows substrate regions to extract independently. Note: Currently this may require copying the "isosub" layer up through the entire hierarchy to the top level for the extraction to work correctly, pending a commit of ongoing work to enhance the substrate extraction method in magic.
  
• posted: July 5, 2021 at 3:00am     version: 1.0     revision: 189
  Fixed bugs with retrieving files in check_density.py and generate_fill.py, syntax fixes for check_antenna.py
  Fixed bugs with retrieving files in check_density.py and generate_fill.py, syntax fixes for check_antenna.py, added error checking for .rcfile to all scripts
  Also: Updated version along with merging pull request #135 from Max Chen.
  Also: Changed the seal ring abstract view to a more sensible layout using obsactive to represent the seal ring diffusion, which does not have the problems of raising DRC errors.
  
• posted: July 1, 2021 at 3:00am     version: 1.0     revision: 188
  Additional changes to the foundry_install script. The main issue was that the conditional block that lists what LEF macros needs to write was not excluding the case where "lef" is already a target and so magic does not need to generate any macros. Also, when creating the target list of LEF macros, the "exclude" list was being applied to the macros and not the files. Additionally, when creating macro lists from verilog, CDL, or SPICE sources, the corresponding exclude list should be used.
  fixed bug so that the temp directory is created in the working directory. script also checks if the working directory is writable. script also checks if 'tmp' is an available directory in addition to 'temp.'
  Also: Script now checks if '/tmp' is available instead of 'tmp'
  Also: Updated version to go with the merge of pull request #134 from Max Chen.
  
• posted: June 25, 2021 at 3:00am     version: 1.0     revision: 187
  Corrected the origin of the sky130_ef_top_power_hvc pad (used in the caravan chip padframe).
  Added "annotate" to the installation of sky130_ef_io, as this avoids using the .magic.lef files from the skywater-pdk source, some of which have errors due to having been built with an older version of magic. Also corrected the custom LEF views for the two top level cells from the FD library to change the LEF class from BLOCK to PAD.
  Also: Removed the nodeinfo.json file which should not be in the distribution files. Added a section to the nodeinfo.json installed file that includes the version numbers for both open_pdks and for magic, so that it is clear what version of magic was used to build the PDK.
  Also: Made a number of changes to the foundry_install script to allow LEF annotation to be used in conjunction with the "compile" or "compile-only" options, indicating that the LEF file sources should only be used to annotate the cells in magic, and that the LEF views generated from magic should then be used to compile a LEF library. The Makefile was modified to use this method for the sky130_fd_io library. Abstract views that had been staged in the custom area as a workaround were removed.
  
• posted: June 24, 2021 at 3:00am     version: 1.0     revision: 186
  Changed the sky130 Makefile io-a recipe to use the LEF sources from the *.lef files instead of *.magic.lef. Otherwise two cells used from the original sky130_fd_io library, the top_xres4v2 and the top_gpio_ovtv2 cells, have incorrect abstract views that are missing pins on one side (an artifact of an old version of magic used to create the abstract views in the library).
  
• posted: June 23, 2021 at 3:00am     version: 1.0     revision: 185
  Added a LEF view of the ESD nFET that exists in the SkyWater I/O library; because it is a top level cell, it does not automatically get an abstract view. However, it is useful for people to use in projects and needs to be abstracted for DRC.
  Updated version to go with the previous commit.
  
• posted: June 22, 2021 at 11:29am     version: 1.0     revision: 184
  Another bugfix
  Updated version with pull request #133.
  
• posted: June 22, 2021 at 9:01am     version: 1.0     revision: 183
  Stop `download.sh` from silently failing\n\nAlso fix issue where is interpreted as a command
  Updated version along with merging pull request #132.
  
• posted: June 22, 2021 at 3:00am     version: 1.0     revision: 182
  fixed VSSD_PAD connection
  Updated VERSION with the merge of pull request #129.
  Also: update pdn configuration to include p&g pins
  
• posted: June 18, 2021 at 3:00am     version: 1.0     revision: 181
  Swapped the layouts for the "clamped" vs. the "clamped2" cells (power pad + overlay + clamp connections), which were reversed with respect to the netlists. The .mag, .gds, and .lef cells were swapped, while the .spice, .cdl, and .v cells/modules remain as-is. Also updated the .mag files, which were out of date (although they are unused by the installation).
  Updated the version with the last commit.
  
• posted: June 16, 2021 at 3:00am     version: 1.0     revision: 180
  Added layouts for the four cells in the HD library that have DRC errors and will not show DRC clean when used in a design. The buf_16 cell is the most important one because the others are unlikely to get used. Also reworked the "exclude" option on foundry_install.py so that it can be used to substitute in alternative cells for processing, like is being done with the abovementioned cell layouts. Also added an "include" option that is similar to "exclude"; it is not currently being used.
  Revert "Added layouts for the four cells in the HD library that have DRC errors and will
  Also: Partial update from the reverted commit: Added the GDS files (which are not being installed for now), and corrected a command in the Makefile that was under the wrong recipe. Changed a message in foundry_install referring to magic 8.2 to convey the proper meaning of "8.2 or better". Updated the LEF files for the I/O pads, which did not get updated along with the SPICE and GDS files, but have been corrected like the others by separating the pad and core nets of the power supply pad cells.
  
• posted: June 15, 2021 at 3:00am     version: 1.0     revision: 179
  Corrected pin connections in the verilog for sky130_ef_io (pins for two cells incorrectly labeled while splitting the pad and core pins on the power pads).
  Added the "fakediode" cell to the list of cells that are ignored by netgen during LVS, since it contains no devices and so gets optimized out of the extracted layout netlist.
  
• posted: June 13, 2021 at 3:00am     version: 1.0     revision: 178
  Slight optimization to the SRAM macro install, which allows the SPICE netlists to be renames through a filter script instead of calling out each file in the Makefile. That prevents the Makefile from having to be updated whenever the SRAM macro repository changes.
  
• posted: June 12, 2021 at 3:00am     version: 1.0     revision: 177
  This update changes the way that 3rd party repositories are pulled, by using (a shallow) git clone instead of pulling a tarball. That allows the commit hash of every repository pulled to be queried and saved in the .config/nodeinfo.json file for reference. Also in this update: Corrected the diode device in the diode cell in the HVL standard cell library. Corrected the build sequence for the I/O library, which was causing the addition of the SPICE netlists for the I/O pads to be missed.
  Added a command "ext2spice scale off" to the magic startup file which will prevent people from unknowingly generating netlists with the scale option in them, which conflicts with SkyWater's scale option inside the model files.
  
• posted: June 10, 2021 at 3:00am     version: 1.0     revision: 176
  A number of changes, mostly to the SPICE libraries and netlists in support of Xyce (without compromising support for ngspice). Also: Additional Monte Carlo parameters were found in PSPICE format in the models and have been converted to something ngspice-compatible. The 11V NPN GDS cell name was changed to allow correct extraction from magic and prevent shadowing the model name. The Monte Carlo switch parameter behavior was changed again to make a separate set of library sections for mismatch-enabled corners vs. the original corners, which have been configured to have mismatch disabled. This avoids any requirement to add a parameter definition to every testbench for sky130. Xyce compatibility includes changing '$' comments to ';', which is also ngspice compatible, and adding the library section name after '.endl', which is also ngspice-compatible. Complete Xyce support requires a change to the all.spice file and calls to function agauss(), the solution to which has not yet been determined.
  
• posted: June 7, 2021 at 3:00am     version: 1.0     revision: 174
  Some fixes and enhancements to the two helper scripts change_gds_string.py and find_gds_prefix.py. The latter script is probably useless because running the Linux "strings" command is much faster. The former script can now be used with multiple string-replacement pairs in one pass, and has the option "-verbatim" to look for exact string matches only, rather than the usual partial string match that comes from using regsub or the string "replace" method in python.
  
• posted: June 6, 2021 at 3:00am     version: 1.0     revision: 173
  Corrected an error in change_gds_cell that fails to handle the GDSism of a null byte after an odd-length string. Added another helper script called find_gds_prefix.py which can find cells with a prefix as added by magic's "gds write" command when dumping a full GDS library into the output.
  
• posted: June 5, 2021 at 3:00am     version: 1.0     revision: 172
  Modified the magic techfile to implement the correct order of types for the "surround-ok" spacing rules. This goes along with an update to magic (8.3.173) to not try to implement the rule with the types swapped, which is great for basic spacing rules but does not work for surround_ok rules on different planes.
  Added a new script utililty called "change_gds_cell" that can be used to swap one cell for another in a GDS file. It is very simple and does not consider any subcells that might be inside the swapped cell; it is designed for quick ECOs for metal fixes.
  
• posted: June 2, 2021 at 3:00am     version: 1.0     revision: 171
  Updated the sky130.tech file to better handle the HVI-to-LV-nwell DRC rule, accounting for HVI abutting nwell through the use of mask hints. Modified the Makefile to include such an HV mask hint on the high-voltage library level shifter cell, so that it does not generate (fals positive) DRC errors.
  Corrected DNWELL layer generation in cifoutput; the layer should comprise "npn" instead of "pnp".
  
• posted: June 1, 2021 at 3:00am     version: 1.0     revision: 170
  Changed the analog pad (sky130_ef_io__analog_pad) LEF CLASS from BLOCK to PAD.
  
• posted: May 29, 2021 at 3:00am     version: 1.0     revision: 169
  Added a new pad sky130_ef_io__top_power_hvc for the "caravan" chip which instantiates the sky130_fd_io__top_power_hvc_wpadv2 but with approximately three times the width on the metal3 connection between pad and core, for high current supply applications.
  Corrected the verilog for sky130_ef_io, which was not separating the pad and core signals on the sky130_fd_io base power pads.
  Also: Corrected a directional surround rule on vias to include metal resistor, without which it can create weirdly intermittant errors if a metal resistor abuts a via.
  
• posted: May 28, 2021 at 3:00am     version: 1.0     revision: 168
  Update correction for the PNP transistor extraction change done a few commits ago: Missed adding a "generic" fallback extraction method for the PNP transistor if the ID layer is missing. This is especially important as I have not added a script to add the ID layer to the installed layout view that magic uses when instantiating the PNP from the device menu (which I will do in the following commit).
  Made a change to the PNP transistor layouts in sky130_fd_pr so that the layouts have an _rf_ in the name (which they did, originally, except not consistently). This keeps the layout cell from having the same name as the wrapper subcircuit, which would otherwise cause an invalid loop of a subcircuit apparently calling itself. The magic .mag view of this device layout is modified to contain the ID layer specific to the 0p68 or 3p40 devices, so that when extracted from magic, the device has the correct extracted name for the device model's subcircuit wrapper. This should be correct now for the four devices that can be instantiated from magic's device generator.
  
• posted: May 26, 2021 at 3:00am     version: 1.0     revision: 167
  Minor correction to techfile to replace a measurement value in a DRC spacing rule explanation string with the "%d" formatting string, as pointed out by Mark Martin.
  
• posted: May 25, 2021 at 3:00am     version: 1.0     revision: 166
  Modified the tech file to correct the rule cap2m.8, which should apply only to distance to via3 outside of the cap2m area, not inside.
  Added code to the process_params.py script to catch about a dozen or so parameter names in parameters/critical.spice that shadow device names. ngspice does a search-and-replace for parameters so these will destroy the simulation. They are not even used in the models as far as I could discover, so just removing them seems to be the right approach.
  Also: Created a new script that deals with the problem of parameter names in the monte carlo parameter files that shadow names of devices. ngspice does not handle this; this could be an ngspice error, but the best practice is not to have confusing parameter names, so the script modifies the names by stripping off the leading sky130_fd_pr__ from the parameter name so that it no longer conflicts with the device name.
  
• posted: May 21, 2021 at 3:00am     version: 1.0     revision: 165
  Turn on offgrid check in klayout drc
  Updated version with merge of pull request #123.
  Also: Added some missing standard cell libraries to the JSON information file for the PDK.
  
• posted: May 20, 2021 at 3:00am     version: 1.0     revision: 164
  Revised the sky130 Makefile to completely ignore blocks that are not specified for install, instead of running all of the target recipe procedures. This prevents the Makefile from building out directory structures for libraries that will not be installed. It also fixes an error where the make process hits an error and halts if the primitives submodule is not initialized.
  
• posted: May 19, 2021 at 3:00am     version: 1.0     revision: 163
  cdl installation scenarios for both EF_STYLE PDK and regular one
  Updated version with pull request #122.
  
• posted: May 18, 2021 at 3:00am     version: 1.0     revision: 162
  Corrected a hard-coded reference to a magic version number directory for the "EF_FORMAT" version of the OpenLane config.tcl file.
  Modified the configure script to *not* run "realpath" on the local-path variable if dist-path has been specified, since local-path may not even exist.
  Also: Revised the fix_device_models script (again) to correct the resistor to type R and diode to type D (from "X"), and to change the diode properties from "a" and "p" to "area" and "pj". Updated the magic technology file to also write the diodes as low-level devices to match this usage, and with the property names stated above.
  Also: Rebuilt the configure script locally.
  Also: One more change in support of EF_FORMAT, to correct one of the patch files to work with the EF_FORMAT naming convention.
  
• posted: May 17, 2021 at 3:00am     version: 1.0     revision: 161
  Added script to fix the issue with incorrect device names for the parasitic diode and shorting resistor in the skywater-pdk digital standard cell repositories.
  
• posted: May 13, 2021 at 3:00am     version: 1.0     revision: 160
  Corrected the MiM area capacitance value as calculated by the device generator in magic (the actual value is in the device model), from 1fF/um^2 to 2fF/um^2, the typical value given in the PDK reference documentation.
  
• posted: May 9, 2021 at 3:00am     version: 1.0     revision: 159
  Corrected a tiny but very bad typo in the magic techfile which effectively knocked out an entire block of DRC rules. This is why I need a proper set of CI checks! Will modify magic to flag such a typo in the future.
  
• posted: May 8, 2021 at 3:00am     version: 1.0     revision: 158
  Update run_standard_drc.py
  Modified the PNP device patch to additionally change the PNP device pin names to match the layout, which has Base, Emitter, and Collector (previously the SPICE netlist had b, e, c).
  Also: Corrected a naming error in the magic techfile that was writing "05v0" in the device names for PNP and NPN devices instead of "05v5", resulting in a name that matches neither device models, or device names in the netgen setup file for LVS.
  
• posted: May 6, 2021 at 3:00am     version: 1.0     revision: 157
  Modified the techfile to not add nwell under pfetarea in cifinput when in the SRAM core cell (modification requested by Jesse Cirimelli-Low).
  
• posted: May 5, 2021 at 3:00am     version: 1.0     revision: 156
  Complete implementation of monte carlo simulation. Enables the scripts that convert the statistics blocks in the model files into ngspice-compatible syntax, both for mismatch parameters (inside the model definitions) and process variation (in .param lines outside the model definitions). Added new block name "mc" for use with the ".lib" command to enable the models with process variation instead of a corner model. Use of ngspice now requires that every testbench set ".param mc_mm_switch=0|1" to disble or enable the parameter mismatch, since the mismatch setting is independent of the corner model used.
  Updated the OSU library URLs, which had the primary branch renamed from "master" to "main", with a corresponding change to the name of the tarball that gets downloaded by open_pdks.
  Also: Corrected a couple of errors in the foundry_install.py script for various one-off cases; corrected an "if" statement syntax in the sky130 Makefile.
  Also: Corrected the patch file for the PNP transistor model, which needed to be updated after changing the monte carlo switch parameter name.
  Also: Corrected the PNP model patch (again, differently, and moved it back to its original location). Added a few lines that remove the extraneous statistics block from the 3.4x3.4 PNP model file, so that the mismatch parameter handling script won't fail on it.
  Also: Fixed the issues with the PNP bipolar transistor. Pulled the 3.4x3.4 device layout from original sources, and fixed the device names to be consistent.
  
• posted: May 4, 2021 at 3:00am     version: 1.0     revision: 155
  Added scripts to convert the statistics blocks to monte carlo parameters that are compatible with ngspice syntax. 1st attempt; application of the scripts is commented out in the makefile. Under test and review.
  
• posted: May 3, 2021 at 3:00am     version: 1.0     revision: 154
  Apparently didn't commit the change to the configure script after updating configure.ac in the commit two days ago.
  
• posted: May 1, 2021 at 3:00am     version: 1.0     revision: 153
  Changed the sed scripts in the sky130/Makefile to put a backslash after the "a" command, as this appears to be compatible with more variations of the "sed" command on different OS versions.
  The Makefile sed scripts for xschem still fail on OS X, which appears to be syntactically different from other versions of sed. Seems to require a newline after the a\ command.
  Also: Stopped futzing around with trying to make "sed" work with OS-X and instead just revised the configure script to autodetect "gsed" vs. "sed" and preferably use the former.
  
• posted: April 30, 2021 at 3:00am     version: 1.0     revision: 152
  Added several patches and corrections to the device models: Uncommented the poly resistor model definition (known issue for some time), added subcircuit definitions for the high voltage pdiff and ndiff resistors (including parasitic diode devices at each terminal, as done for the low voltage pdiff/ndiff resistors), and replaced the resistor names in the HVL digital standard cell library (since there was no subcircuit model for these, the names did not get remapped).
  Corrected the height/thickness stackup in the extraction section of the magic techfile to reflect the fact that there is no polyimide layer on top of the whole chip, leading to a lower position of the RDL layer.
  
• posted: April 29, 2021 at 3:00am     version: 1.0     revision: 151
  Small change to the configure script to properly mark the options that are disabled by default when using 'configure --help'.
  Updated the README information to reflect the recent changes in the enable/disable options for configuration, and to match the documentation on the website.
  
• posted: April 28, 2021 at 3:00am     version: 1.0     revision: 150
  Updated the sky130 Makefile to take advantage of the "gds unique" option just added to magic version 8.2.60; this prevents issues with the SRAM macro installation by preventing duplicate cell names, since many of the cell names are reused among all the macros.
  Modified the Makefile to correct several errors when installing with the "ef-style" option. This required splitting the patch file for sky130_fd_pr into two so they could be applied separately to files in the libs.ref path and the libs.tech path.
  Also: Swapped the collector and emitter entries on the bipolar extraction devices in magic, because they were incorrect and would end up reversed in the extracted netlist.
  Also: Corrected the other problem with the PNP bipolar, which is that the model has a substrate pin defined, although the process requires that the collector of the PNP must be tied to the substrate, so the device cannot have an independent substrate.
  
• posted: April 27, 2021 at 3:00am     version: 1.0     revision: 149
  Corrected typos in the name of the macro for sky130_ef_io__analog_pad in the custom LEF file.
  
• posted: April 25, 2021 at 3:00am     version: 1.0     revision: 148
  Made some chages to the "run_standard_drc.py" script so that it can be run on a file that is in a non-writeable directory. In that case, the current directory will be used for the DRC script file and the output text file.
  
• posted: April 23, 2021 at 3:00am     version: 1.0     revision: 147
  Added a placeholder subcircuit definition for sky130_fd_io__condiode, because otherwise simulations involving I/O cells will fail.
  Modified the configure script to allow 3rd party libraries to be either installed by default (requiring --disable) or ignored by default (requiring --enable). Moved the SRAM library to the "ignored by default" list because it takes so long to build. Added all of the OSU standard cell libraries (hs/ms/ls each for 12T, 15T, and 18T). Added a straight-through analog pad for high-speed I/O, especially for the "caravan" analog variant of the "caravel" harness chip.
  
• posted: April 21, 2021 at 3:00am     version: 1.0     revision: 146
  Completed the unfinished DRC check script, renamed it to "run_standard_drc.py", and added a preliminary antenna rule violation check script.
  Corrected the terminal resistance values for the xhigh_po (2000 ohms/sq. nominal) resistor, which were set to some old value left over from cut-and-paste and not updated like the high_po (320 ohms/sq. nominal) resistor. This error causes major discrepancies for the calculated device value when W is short. Note that this only affects the displayed value of the resistor in the device generator; the device simulates according to the correct width and length.
  Also: Updated the technology file to better represent the exact DRC errors for the RPM layer, and updated the device generator to generate the precision resistors with either nwell or p-sub (or HV version of either) underneath, with appropriate spacing.
  
• posted: April 6, 2021 at 3:00am     version: 1.0     revision: 145
  Added a new type "isosub" to the magic techfile, for isolating areas of the p-substrate from the rest of a circuit.
  
• posted: April 1, 2021 at 3:00am     version: 1.0     revision: 144
  Added support for the 3.3V native nFET device (in addition to the 5.0V native nFET device). There does not appear to be any physical difference between these devices, but they have different length and width ranges in the model bins, and have different models.
  Added cifinput handlers to track NWELL and HVI and pull them up into higher levels of the hierarchy so that they combine properly with some geometry used in the I/O cells to patch over the top.
  
• posted: March 31, 2021 at 3:00am     version: 1.0     revision: 143
  Added the (corrected and verified) netlists for sky130_fd_io as a custom addition to the library (as the pull request mechanism for the libraries is in limbo). Corrected the netlists for the sky130_ef_io pads with overlays to correct the clamped and clamped2 pads, which were swapped, and to separate the pad net for each of the power pads, which is separated from the core by a ring of m5 resistor, and so won't produce correct LVS if merged by name.
  
• posted: March 26, 2021 at 3:00am     version: 1.0     revision: 142
  Modified cifinput section of the magic tech file to always draw type "pwell" in deep n-well P regions; otherwise isolated bulk nFET devices are not extracted correctly.
  Modified the magic techfile "cifinput" section to always draw a pwell layer under N diffusion and P tap. This is not strictly necessary but will prevent extraction errors when circuits are placed in a deep nwell area.
  
• posted: March 19, 2021 at 3:00am     version: 1.0     revision: 141
  Corrected the sky130 Makefile so that if the repository is checked out or built from a zip file or tarball, and is not itself a git repo, then the revision number will get set from the VERSION file (like it used to be) instead of relying on "git describe" which won't return anything.
  Added "set ng_nomodcheck" to spinit, which is supposed to make loading models somewhat faster.
  
• posted: March 16, 2021 at 3:00am     version: 1.0     revision: 140
  Added spinit file under custom/models to get the correct startup options for ngspice. Made a "create_project" script to create some basic project subdirectories and seed them with links to the appropriate startup files. Modified the "preproc" script so that it maintains the file permissions from input to output.
  
• posted: March 14, 2021 at 3:00am     version: 1.0     revision: 139
  Modified the Makefile to install some of the common scripts into the destination at /usr/share/pdk. Corrected the patch from xschem for sky130_fd_pr, which was applied backwards.
  
• posted: March 10, 2021 at 3:00am     version: 1.0     revision: 138
  Added hooks to the Tcl code in magic for schematic-to-layout conversion, adding an "Import SPICE" menu item to the magic setup when the PDK is installed. Only lightly tested, and needs some additional development.
  
• posted: March 9, 2021 at 3:00am     version: 1.0     revision: 137
  Added carry select adder mapping files
  Updated version with the merger of pull request #118 from Manar.
  
• posted: March 4, 2021 at 3:00am     version: 1.0     revision: 136
  Slight extension to the "options=" option to allow the value to be a Tcl expression instead of a filename, in case only a one-line addition is needed to a script.
  
• posted: March 3, 2021 at 3:00am     version: 1.0     revision: 135
  Add the fake diode to the list of 'parallelizable' cells
  Updated version along with pull request #117.
  Also: Swapped the PIN and TXT layer purposes so that they match the "usual" use in the SkyWater GDS files. Note that the SkyWater standard cells are done in a weird way with the pin geometry on a PIN purpose but the pin text on a TXT purpose. The cifinput style sky130(vendor) will work to read in these schizophrenic labels. Magic will not write out this kind of pin label, but the Calibre deck appears to be able to handle what magic writes out.
  
• posted: March 2, 2021 at 3:00am     version: 1.0     revision: 134
  Modified the netgen setup to allow parallelizing of a number of the standard cells (such as fill, antenna, decap, and tap).
  
• posted: February 27, 2021 at 3:00am     version: 1.0     revision: 133
  Added the sky130_sram_macros library from the github/efabless repository. These are used in the Caravel chip, but there is no place where the underlying cells are made available in the PDK, making it impossible to run LVS, DRC, or do simulation at anything other than a black-box level of the whole SRAM block.
  Corrected the GDS read of the SRAM cell so that the weird parasitic device formed between DIFF and TAP under a grounded gate is interpreted as type npd, which is the type that has a model that supposedly is for this device. I attempted to add extraction methods specifically for the parasitic MOScap-type devices in the SRAM cell. Both now generate error messages when extracting. The DIFF/TAP-under-gate device now extracts with the correct length and width. The pFET MOScap has the correct width but not length (probably counting the sides).
  Also: Made one modification from the last commit, which is to not make a special entry for the MOScap pFET device. This prevents the terminal connections from being in error, but now both the L and W are wrong, albeit by a very small amount. This will need to be investigated, as well as the apparently innocuous error message on the nFET device.
  Also: Updated the VERSION.
  
• posted: February 26, 2021 at 3:01am     version: 1.0     revision: 132
  Modified the Makefiles to include a "make uninstall" to remove an installed PDK.
  Corrected two errors in handling SRAM core cell devices: (1) the npass devices were getting eliminated, and (2) the smaller parasitic ppu devices were getting eliminated. The first one was unintentional and due to copying a set of operators to the wrong place; the second one was probably intentional, but the smaller parasitic devices do have a characterized model and should be extracted. However, one of the parasitic devices in the dual port SRAM layout does not match any valid characterized device model bins, and the model bins may need to be extended.
  
• posted: February 25, 2021 at 3:00am     version: 1.0     revision: 131
  update the rest of the std cell libraries openlane configs to a working state
  Add SUBCKTs for some of the missing pads/fillers
  Also: Updated VERSION along with merging pull requests #115 and #116.
  
• posted: February 24, 2021 at 3:00am     version: 1.0     revision: 130
  Fix for older versions of bash
  Updated VERSION with the merge of pull request #114
  
• posted: February 23, 2021 at 3:00am     version: 1.0     revision: 129
  Update the exclude lists to match the new mapping of muxes to size 1
  Incremented VERSION to go along with pull request #113.
  
• posted: February 20, 2021 at 3:00am     version: 1.0     revision: 128
  Corrected the sky130 setup file for netgen so that the poly resistor is treated like the metal resistors (all of them use "R" type devices in SPICE, not "X" subcircuits), and corrected the pin names used for permuting to "end_a" and "end_b", as netgen sets them for "R" type devices.
  
• posted: February 18, 2021 at 3:00am     version: 1.0     revision: 127
  Updated metal1 to metal4 fill to increase pattern spacing for coarse patterning from 0.6um to 0.8um to reduce the maximum pattern density from 59% to about 51%, especially as being so close to the limit was pushing metal4 full-chip density over the limit due to the wide m4 buses on the I/O cells.
  Map to the smallest mux by default,
  Also: move all probe/c cells to the drc_exclude list
  Also: Updates to VERSION to go along with pull requests 111 and 112, and an update to the check_density script.
  Also: OL: Decrease the tapping distance to 13um
  Also: Corrected an error in the density check script, and updated the fill generation script to include an option to run in distributed (multi-processing) mode.
  Also: One correction to the fill generation; otherwise, the top level layout gets an ID layer dropped on it that's not supposed to be there.
  Also: Added a modified decap_12 cell (again)---the previous one caused FOM fill issues, so this one just removes LI to solve the LI density issue without altering the FOM layers (DIFF).
  
• posted: February 16, 2021 at 3:00am     version: 1.0     revision: 126
  Continuing updates to the xcircuit installation for sky130.
  Further refinement on the xcircuit libraries, especially for sky130_fd_pr.
  Also: More refinements on xcircuit setup for sky130_fd_pr.
  
• posted: February 15, 2021 at 3:00am     version: 1.0     revision: 125
  Continued work on the xcircuit libraries for sky130.
  Corrected missing rules for poly to tap spacing that were caused by revising the rules to prevent DRC errors being flagged on varactors, but missing the rules for ptap.
  Also: Updates to the xcircuit library for sky130_fd_sc_hd.
  
• posted: February 14, 2021 at 3:01am     version: 1.0     revision: 124
  Fixes to the (work in progress) xcircuit installation, and added a patch file for fixing sky130_fd_pr, created from the patch file in xschem_sky130 but applied between the build and installation, so that it does not directly patch the skywater-pdk repository.
  Made significant updates to netlist_to_layout.py (although still needs some additional refinement and testing). Corrected an error in the pfet device defaults in the sky130.tcl PDK for magic.
  
• posted: February 13, 2021 at 3:00am     version: 1.0     revision: 123
  Added preliminary (and unfinished) xcircuit integration.
  
• posted: February 12, 2021 at 3:00am     version: 1.0     revision: 122
  Added adder mapping files for yosys
  Updated VERSION along with pull request #107 from Manar Abdelaty. Also revised the Makefile.in file to loop over install files for openlane instead of enumerating each one.
  Also: Corrected the automatic installation of third-party tool setups and libraries (for now, specifically the xschem setup and the alphanumeric layout library), and cleaned up the instructions to make it clear how to do the installation in the most common case.
  Also: Correction to a typo in staging_install.py from the last commit.
  Also: Added a hybrid fill cell size 12 that is the size of a decap_12 but has half the amount of decap; the remainder of the cell is made up of a fill_4 and a fill_2. This can be used for fill density planning in digital synthesis layouts.
  Also: Corrected the GDS file for the custom fill-12 cell.
  Also: Revised the build system so that all packages that are to be automatically downloaded and installed are done during "make" instead of during "configure". This includes moving URLs into the Makefile, moving actions like untarring into the download script, and replacing the "information" file for the PDK with a custom download script.
  Also: Made some clarifications in the README file.
  Also: Set KLayout tech dbu to 0.005um
  Also: Revised the exclude lists used in openlane
  Also: Further refined the configuration options to make the alphanumeric library and xschem setups enabled by default, and to make the local install location /usr/share/pdk/ by default. So the configuration line has been simplified to "configure --enable-sky130-pdk".
  Also: Added a sed script to modify the xschemrc file when copying to the staging area. This is an incomplete implementation, but lets xschem start up correctly.
  
• posted: February 9, 2021 at 3:00am     version: 1.0     revision: 121
  Fixes and reorganization of the KLayout DRC deck
  Updated VERSION with pull request #105 from Ahmed Ghazy.
  Also: Once again updated the density pattern generator for what I hope are the final tweaks.
  Also: Perform substitution on the PDN config side
  
• posted: February 8, 2021 at 3:01am     version: 1.0     revision: 120
  Additional fine-tuning of the fill generation of all metal layers under metal5 to meet the corrected density requirements from SkyWater (minimum clear area = 40%, or maximum fill density = 60%).
  
• posted: February 7, 2021 at 3:00am     version: 1.0     revision: 119
  Additional correction to the density check script to update the density limit values in the sub-area checks (in addition to the total area checks, which were fixed in the previous commit).
  
• posted: February 6, 2021 at 3:00am     version: 1.0     revision: 118
  Add yosys mux mapping.
  Updated VERSION along with the last pull request #104 from Amr Gouhar.
  Also: Adjusted LI coarse fill spacing from 600 to 650 to reduce the maximum fill amount from about 65% to about 60%.
  Also: Updated clear area density limits based on input from SkyWater.
  
• posted: February 5, 2021 at 3:00am     version: 1.0     revision: 117
  [openlane] set default cell pad to 4
  [openlane] add pointer to no synth list -- first step to design specific lists
  Also: [yosys] copy latch mapping..
  Also: Added some complexity to the NPC implant layer generation to avoid a somewhat common case of bridging shapes being placed too near to non-poly LICON contacts.
  Also: Updated the sky130gds.tech file to include an assortment of DRC checks that the DRC deck in the "standard" sky130.tech file does not do. Added off-grid checks as well as basic checks on implant layer geometry. The off-grid checks require the most recent version of magic, so the "requires" line was added to the tech file.
  
• posted: January 29, 2021 at 3:00am     version: 1.0     revision: 116
  Corrections and updates to the bump-bond technology file and accompanying script procedures.
  Added "mask-hints" output capability for layers LVTN and HVTP, which are used in standard cells.
  
• posted: January 28, 2021 at 3:00am     version: 1.0     revision: 115
  Fix fakediode name
  Correct 'fd' -> 'ef' in fakediode
  Also: Updating VERSION with pull requests 101 and 102 from Ahmed Ghazy.
  Also: Added IRSIM parameter files to libs.tech/irsim/ as part of the installation.
  Also: Added a set of Tcl routines for generating bump bonds for the Micross post-processing.
  
• posted: January 27, 2021 at 3:00am     version: 1.0     revision: 114
  Don't recursively expand SKYWATER_PATH
  Updated VERSION
  Also: Fix fakediode views
  
• posted: January 25, 2021 at 3:01am     version: 1.0     revision: 113
  Applied patch from Mohamed Gaber that fixes the issue of the configuration script not doing tilde expansion on paths in the configure command line. This patch uses python3 and is cross- platform (existing code used "readlink -f" and so also had problems on Mac OSX). Also changed the configuration script so that the value for --enable-sky130-pdk can have the libraries/ directory on the end or not, and it will find the path regardless.
  Updated VERSION.
  
• posted: January 23, 2021 at 3:01am     version: 1.0     revision: 112
  Force GDS reads in magic to ignore layer 236:0, which is some kind of undocumented outline marker.
  Added verilog file for the "fake diode" cell used by openlane in sky130_fd_sc_hd.
  Also: Added "random seed" to the magic startup file so that the behavior of adding unique prefixes to vendor GDS dumps is truly randomized.
  
• posted: January 22, 2021 at 3:01am     version: 1.0     revision: 111
  Add missing MINENCLOSEDAREA as patches for now...
  Check for 'patch' in configure script
  Also: Updated version after merging pull request #95 from Ahmed Ghazy.
  
• posted: January 20, 2021 at 3:00am     version: 1.0     revision: 110
  Add a KLayout report description
  Merged pull request 94 from Ahmed Ghazy.
  
• posted: January 19, 2021 at 3:00am     version: 1.0     revision: 109
  Some fixes to sky130A klayout DRC script
  Merged pull request #93 from Ahmed Ghazy (Klayout DRC setup file).
  
• posted: January 17, 2021 at 3:00am     version: 1.0     revision: 108
  Corrected density check script, and corrected the LI fill generation to meet the MR manufacturing requirements.
  add klayout lydrc from @laurentc2
  Also: auto generate drc run_set
  Also: The lazy workaround for the utf-8 encoding issue
  Also: Updated VERSION to go along with the merge of pull request 91 from Amr Gouhar.
  Also: Modified the metal5 density pattern generation to make up a small density deficit caused by the spacing of openlane top-level metal power routing.
  
• posted: January 15, 2021 at 3:00am     version: 1.0     revision: 107
  Corrected the fill generation script to avoid dropping fill outside the chip area if the chip area is not an exact multiple of the check step. Also added a density check script for running on final GDS with fill (the output of the fill generation script).
  add GDS_FILES pointer and a KLAYOUT_TECH, PROPERTIES pointers
  Also: add @laurentc2 klayout setup to replace the current klayout setup
  Also: Update config.tcl
  Also: Updated VERSION to go along with pull request #90 from Amr Gouhar.
  
• posted: January 13, 2021 at 3:00am     version: 1.0     revision: 106
  Corrected the metal5 fill patterning, as the size of the fill shapes was changed but the associated shrink/grow rule was not adjusted along with it.
  
• posted: January 12, 2021 at 3:00am     version: 1.0     revision: 105
  Corrected an error in the magic techfile which was left over from an early implementation of MiM caps and will erase the metal layers from a MiM cap on GDS read. Also: Corrected the netlists for the I/O power and ground cells to work around an error with the OGC* pins, which are internally connected. Modified the netgen setup file to allow the number of columns to be adjusted through use of an external environment variable NETGEN_COLUMNS.
  Removed a wayward line from the tech file that was a non-syntactical marker and should not have been committed.
  Also: Tweaked the fill pattern slots operators to ensure a maximum fill density on a clear area that is less than the specified DRC maximum. For M5, increased the fill shape size to exceed the specified DRC minimum---this rule may need further tweaking.
  Also: Added a cifoutput section called "density" for more efficient density checking.
  
• posted: January 9, 2021 at 3:00am     version: 1.0     revision: 104
  Corrected the sky130_ef_io__vdda_hvc_clamped_pad cell, which had the clamp overlay cell flipped left-to-right, which swaps the proper connections to the clamp.
  Created the wrong filename for the GDS of the custom sky130_ef_io in the last commit. Also for this commit: The equivalent VSSA pad to the one corrected in the last commit also needed to be modified.
  
• posted: January 7, 2021 at 3:01am     version: 1.0     revision: 103
  Modified the magic techfile to remove the CELLRING templayer from the GDS output, as it is being replaced by the "mask-hints" method. Added mask hints to the top_gpiov2 cell from the Makefile for sky130A so that the GPIO cell does not generate bit trash on the HVI mask due to remaining inconsistencies in the way the GDS for the cell is read into magic. Updated VERSION and also the required magic version for using this tech file (8.3.111), since only revision 111 will correctly handle the mask-hints method.
  Corrected the sky130 Makefile to put the special handling of the GPIO cell with "insert_property.py" below the installation of the library, or else the file to be modified won't be there. Corrected a handful of places in the common scripts where "/bin/env" was used instead of the more common "/usr/bin/env".
  Also: Added parameter handling in extraction of MOSFET devices for source and drain area and perimeter.
  Also: Changed the layer assignments for the fill layers to match what SkyWater expects. Added a fill layer generation and layers for local interconnect fill.
  
• posted: January 6, 2021 at 3:01am     version: 1.0     revision: 102
  Corrected the sky130_ef_io.gds file to correct the position of the overlay cell on the vccd_lvc_clamped2 pad. Updated the LEF files of the clamp-connected pads, which were out of date with respect to the GDS file.
  Once again edited the same clamp-connected pad layouts, this time to remove a metal wide-spacing DRC error caused by the additional metal1 connection to the back-to-back diodes.
  
• posted: January 5, 2021 at 3:00am     version: 1.0     revision: 101
  Initial None setting for tclscript to prevent referencing a non- existent variable later in the script. Merges pull request #88 from Ahmed Ghazy.
  
• posted: January 4, 2021 at 3:00am     version: 1.0     revision: 100
  Minor update which allows a custom Tcl script to be inserted in the GDS import script when generating magic cells. The script can then take advantage of the "flatglob" option to flatten specific cells on input, which can be used to work around database incompatibility issues when importing GDS into magic.
  
• posted: January 2, 2021 at 3:00am     version: 1.0     revision: 99
  Made a very minor change to the README file to reflect the new configuration option name "--enable-sky130-pdk" that replaces "--with-sky130-source"; plus I noticed that the README file also listed the incorrect option "--with-local-path" which should be "--with-sky130-local-path". No functional change was made to the repository.
  
• posted: December 31, 2020 at 3:01am     version: 1.0     revision: 98
  Modified the corner cell in the padframe corner overlay to add "obsactive" in the corner along with the existing "fillblock" to prevent the generation of fomfill in the corners, since the "fillblock" layer only blocks metal fill.
  Changed the magic tech file so that it recognizes "obsactive" and will translate it to an FOM waffle drop datatype, so that the change made to the corner pad in the last commit actually works as advertised. Rebuilt the custom pad extension GDS library with this change. Also corrected an error in the tech file where a missing comma would cause polysilicon not be recognized during fill pattern generation, leading to collisions between poly and poly fill shapes.
  Also: Removed the name "licon" from the magic techfile, as it is used incorrectly compared to the SkyWater documentation, and there is no concept in magic of a single contact type between local interconnect and poly, diffusion, or tap. Also changed some of the CIF names from the SCMOS naming conventions to SkyWater's; namely HVI instead of THKOX, NSDM instead of NPLUS, and PSDM instead of PPLUS. Hopefully this eliminates the worst inonsistencies and confusions.
  Also: Changed one instance of licon in the sky130.tcl PDK file to mcon.
  
• posted: December 30, 2020 at 3:02am     version: 1.0     revision: 97
  Added a full fill generation script which breaks a design up into tiles for faster, more memory-efficient processing. This includes some changes to the techfile to create two variants for the fill patterning, one that should be used for a full-chip pattern, and one to be used with the script. Also removed the patch file from yesterday's commit.
  Added the fill generation to the make script so that it gets installed in the magic setup section of the PDK.
  Also: Corrected one typo in the fill generation script.
  Also: Remove 0.015um met5 notch on {,dis}connect cells
  Also: Fill violating met1 holes in the clamp overlays
  Also: Update routing version of the IOs
  
• posted: December 29, 2020 at 3:01am     version: 1.0     revision: 96
  A number of changes to the magic techfile: (1) Added more mask-hints operators to the cifoutput section, to cover the ID layers, (2) merged the "sky130" and "vendorimport" styles of cifinput into a single style "sky130" with variants "sky130()" and "sky130(vendor)". This prevents mistakes caused by making changes to one of the styles while failing to make the corresponding change in the other, of which several exmples were discovered when doing the merge.
  Corrected one error with an overlay pad, which was colliding with via3s in different locations on one of the two cells it was being overlaid on, by creating a separate overlay cell for each pad. Corrected two other cells, one with the clamp overlay and one with just the power overlay, which used the wrong overlay cell.
  Also: Additional support for automatically searching standard places for repositories before attempting a download.
  
• posted: December 27, 2020 at 3:00am     version: 1.0     revision: 95
  First draft of a complete CDL/SPICE netlist for the sky130_ef_io cells (supplementary to sky130_fd_io). Previously these were black-box stub entries. Now they make references to the SkyWater cells, although those cells (or at least the SPICE netlists of them) are in the scratch repository and not yet pushed to the public repository.
  
• posted: December 25, 2020 at 3:00am     version: 1.0     revision: 94
  Changes from Donn to enhance the configuration script to allow specific tools to be enabled or disabled for setup installation.
  Changes to the techfile and netgen setup file in support of the sky130_fd_io I/O library; the area detection for areas of native Vt FETs was reduced from 1um to 0.35um because the former can overlap other areas and result in invalid transistor devices. The netgen setup added the I/O tap cell to the cells to exclude from matching (this change may be temporary).
  Also: Moved the fill type GDS import into the regular GDS import instead of in its own special section. Created new types for poly and FOM fill. Created type "fillblock4" to block all fill up to but not including metal5.
  Also: Updates from Donn to enable open_pdks to clone and install repositories as needed for the installation. Note change to configure script option for the path to the SkyWater PDK (if not being automatically installed in a local path).
  Also: Ran last commit from the wrong directory and didn't catch most of the modified files.
  Also: Corrected a comment line in the Makefile to match the text of the option in configure.
  
• posted: December 22, 2020 at 8:18pm     version: 1.0     revision: 93
  Corrected the netgen setup file, which was missing the nfet 5V native vt transistor in the list of transistors. Added an entry to ignore the cell "condiode", which appears in schematics but cannot be extracted (due to apparent lack of defining characteristics). Corrected a comment in the magic techfile (non-functional, no impact on use of magic).
  Added the netlist_to_layout python script that reads a SPICE netlist and creates a device generator Tcl script that can be run through magic to create all the devices, subcircuits, and ports as a starting point for a layout. This has just been dropped in without any attempt to integrate; it needs work to support both directory structure styles from open_pdks (EF_STYLE 0 or 1), and for the schematic checks and automatic netlist generation, needs to be switched from electric to xschem---which will have to wait on xschem integration in open_pdks (coming soon for sky130). The schematic tool independent part of this (SPICE to magic) needs to be split out as an option that can be called independently.
  Also: Restore I/O bus fillers from 0ad7fc94a
  Also: PAD GROUND -> PAD POWER
  Also: Remove leftover pin declarations in a clamped pad
  Also: Added ESD devices for the 5V nFET and pFET, which are essentially just marker layers used for LVS; however, as these are the devices with angled gates, they can be used
  Also: Added support in the magic tech file for ESD devices of the 5V nFET and pFET varieties. These are essentially just standard 5V FETs with a marker layer used for LVS purposes; however, as these are the devices with angled gates, they can be used to suppress DRC errors in the device layouts (which has not yet been done).
  Also: Reapply connect/disconnect cell fixes from fe967d6
  
• posted: December 21, 2020 at 3:01am     version: 1.0     revision: 92
  Added some devices to the sky130_setup.tcl file that had not been added to the netgen setup since they were added to the magic techfile extraction section.
  
• posted: December 20, 2020 at 3:00am     version: 1.0     revision: 91
  Added eight more overlay combination cells; these create connections between the clamp circuits and the buses as well as between the pad and buses. There are very many possible combinations, but these have been limited to a smaller set used for the caravel chip. Also updated the LEF views with magic 8.3.100, where a correction was made to an error that missed obstructions outside of the abutment bounding box when doing "lef write -hide". verilog netlists have been updated with the new combination cells. The CDL netlists have been updated with at least black-box views to assert pin order; and the full CDL netlist has been provided where the CDL exists for the cell in skywater-pdk-scratch (development build of sky130_fd_io).
  Forgot to update VERSION in the previous commit.
  Also: Ignore fill and tap cells in device level LVS
  
• posted: December 19, 2020 at 3:00am     version: 1.0     revision: 90
  Corrected the widespacing rules in the techfile so that they are triggered by metal width > 3um instead of metal width >= 3um.
  Added a filter to transform the sky130_ml_xx_hd library from metal1 to metal5 and scale the characters up by a factor of 12 so that they will be DRC clean for metal5.
  
• posted: December 18, 2020 at 3:00am     version: 1.0     revision: 89
  Added support for Paul Schulz's alphanumeric font character library for magic, including a modification of the text2mag.py script for use with the open_pdks installation.
  
• posted: December 17, 2020 at 3:00am     version: 1.0     revision: 88
  Updated the technology file to use the "requires" keyword, which will force magic to be updated to 8.3.99. Going forward, it will be much easier to deal with version requirements for magic when using the technology file, as the technology file can specify the version of magic required to use it. Also: Added the mask-hints operator introduced in magic 8.3.98. This allows automatically- generated mask layers to be supplemented by geometry specified as a cell property.
  Modified the magic tech file so that fill patterns are all generated on purpose 28 as specified by SkyWater.
  
• posted: December 15, 2020 at 3:00am     version: 1.0     revision: 87
  Added some exclusions for COREID areas to cifinput recipes that are copied up the hierarchy (to cope with composite layers being spread across different cells), as the core cells have contact cuts over space that cannot be distinguished from the above.
  
• posted: December 12, 2020 at 3:00am     version: 1.0     revision: 86
  Corrected the handling of POLYTXT and POLYPIN layers on GDS reads, so that a pin label over a gate does not overwrite the transistor with poly only.
  Added I/O pad clamp connection overlay cells to the I/O set. Updated a few rules for the GDS input of SRAM core cells, from a patch by Matt Guthaus.
  
• posted: December 11, 2020 at 3:00am     version: 1.0     revision: 85
  Added SITE and SYMMETRY entries for the sky130_ef_sc_hd__fakediode_2 LEF view.
  Add the other .lib needed to cover all HVL cells
  Also: [openlane] Parameterize the PDN configs even more
  
• posted: December 10, 2020 at 3:00am     version: 1.0     revision: 84
  Linking from None fix
  Updated VERSION to go along with the pull of the CI yaml file for CloudV.
  Also: Added types corenvar and corepvar to represent the ends of tap layers in the SRAM core cells that are tucked under poly and are not considered devices by SkyWater, but just extracted as parasitic cap. Note that the parasitic cap values for these layers still need to be specified in the extract section.
  Also: Corrected the sky130_ef_io.v verilog library to replace references to the deprecated cell sky130_fd_io__top_power_hvc_wpad with the replacement sky130_fd_io__top_power_hvc_wpadv2.
  Also: Added a fillblock shape in the corner of the I/O pad wrapper in sky130_ef_io so that the corner area with the alignment marking does not get covered in fill shapes during fill generation.
  Also: Generated GDS from the corner pad with fillblock after realizing that the installed file comes from the GDS, not the .mag file, so that changes to the .mag file are meaningless.
  Also: Revised one core locali rule that was modified yesterday that causes false-positive errors around contacts.
  
• posted: December 9, 2020 at 3:00am     version: 1.0     revision: 83
  Finalized (I hope) the fill generation output style.
  Corrected the configuration script to correctly handle an absent "dist-path". The previous syntax appears to be incompatible with some versions of bash.
  Also: Corrected the spacing rule for local interconnect in core cells (0.14um), and reverted back to the normal width and spacing rules for coreli because the edge4way rules are unnecessary, and just more confusing to the observer.
  
• posted: December 8, 2020 at 3:00am     version: 1.0     revision: 82
  Modifications to the waffle fill pattern generator output style.
  
• posted: December 4, 2020 at 5:11pm     version: 1.0     revision: 81
  Added a bare wirebond pad structure to the list of cells in the sky130_ef_io library.
  Modified the staging_install script so that an option "-variable" can be passed, such that .mag files in mag/ and maglef/ directories of the libraries will have GDS files point to the PDK by variable reference, e.g., using $PDK_PATH, so that layouts can be made portable.
  
• posted: December 4, 2020 at 3:00am     version: 1.0     revision: 80
  Corrected minor offsets in the metal positions of the special I/O bus connect and disconnect cells that were inherited from errors in the original spacer cells (that were fixed on the last commit).
  
• posted: December 3, 2020 at 3:00am     version: 1.0     revision: 79
  Modified the LEF views of the I/O padring filler cells so that they do not cover the empty area with the metal4 obstruction layer, which causes trouble with DRC and extraction if any active circuitry with wiring up to metal4 is placed in this area.
  Additional corrections to the magic and LEF views of the I/O cells to correct a minor error in positioning of one of the metal5 layers in the abstract view of the filler cells.
  
• posted: December 2, 2020 at 3:00am     version: 1.0     revision: 78
  Added tribuff_map to all standard cells
  Updated revision to go along with the latest pull request merge.
  Also: Changed the "lef" section of the techfile to cast via geometry in an obstruction section (other than vias/contacts below m1) to the base metal layer; otherwise "lef read" screws up the layers.
  
• posted: December 1, 2020 at 3:00am     version: 1.0     revision: 77
  Added tri-state buffer mapping file
  Updated tri-buf name
  Also: Updates needed for the tristate buffer mapping
  Also: control the global_connections section in common_pdn.tcl with a flag
  Also: Updated the revision to go along with recent pull request merges.
  
• posted: November 30, 2020 at 3:00am     version: 1.0     revision: 76
  Added option to the poly resistor to use a high-voltage well for the guard ring.
  Modified PPLUS and NPLUS layer generation operators in the cifoutput section of the magic tech file, as they were missing the grow/shrink operators needed to merge across narrow gaps.
  
• posted: November 28, 2020 at 3:00am     version: 1.0     revision: 75
  Corrected rule poly.9 so that it is not flagged by type "rmp", which is POLY + POLYSHORT, and not POLY + POLYRES, which is what the rule refers to. This prevents false positive errors in the standard cell tap cells, which contain the poly short layer.
  Corrected misspelling "php" to "pnp" in the netgen setup, as pointed out by @yrrapt in github issue #66.
  Also: Corrected the MiM cap rules (some of which were more conservative than necessary because the via surround and spacing rules had not been corrected for the amount of surrounding metal already included in the contact type). Also corrected the Makefile so that it does not fail on attempting "rm -f" on a directory.
  Also: Corrected rule cap2m.8, as it implies that stacked MiM caps may not overlap contacts---which essentially makes them not able to stack. . .
  Also: Removed the rndiff, rpdiff spacing to contact rules, which do not exist in the PDK (required distance is zero; i.e., no overlap, which is enforced by the definition of the magic tile types).
  Also: To go along with the last commit, diffusion resistors must be included in the types that can satisfy the surround rule for diffusion around licon. Also corrected an error in which mvpdiffres was not in the list of types checked for MV diffusion width.
  Also: Revised the code that generates MiM caps in the PDK Tcl scripts, because the DRC rules specifically prevent cap2m overlapping via3; so to make an actual stacked capacitor, the contacts for the lower cap cannot be directly under the first. So the options have been enhanced to allow the contact to the MiM caps to only partially cover the capacitor plate area. Also decreased the spacing from cap plate to contact to the minimum required, and added code to increase that distance as necessary to enforce the minimum metal spacing rule on the capacitor top. Also updated the extraction rule for the diffusion resistor types to match the added subcircuit definitions for both.
  
• posted: November 25, 2020 at 3:00am     version: 1.0     revision: 74
  Add custom I/O wrapper and bus slices (fillers)
  Install fakediode properly
  Also: Add antenna info for sky130_ef_io pads
  Also: Update no_synth.cells
  Also: Update openlane pdngen config
  Also: Updated version to 1.0.73 to go along with the pull request merges.
  
• posted: November 24, 2020 at 3:00am     version: 1.0     revision: 73
  Added the layouts used for DRC ruleset development to sky130/custom/drc/.
  Corrected the "short" model which is actually being called as a subcircuit, not a resistor, from the extraction in magic. Also added a new custom file "diode.spice" which does the same thing for the diodes, which are defined as low-level diode types but are extracted from magic as a subcircuit.
  Also: Corrected "corelocali" layer rules so that magic does not raise various false positive errors when using the layer around contacts and diffusion.
  
• posted: November 23, 2020 at 3:00am     version: 1.0     revision: 72
  Added a new script in common/ "cleanup_unref.py" which removes all parameterized cell layouts from a directory that are unreferenced by any other layout file. These "orphan" cells are commonly left behind when changing parameter values of parameterized cells.
  Corrected the position of "suspendall" in the contact generation routines in the PDK Tcl file for magic, so that those routines do not return while still in the "suspendall" state.
  Also: Corrected magic extraction rule for the high-resistance poly resistors, which are specific to the device width and therefore do not need or take a value W. Corrected a typo in the names of the 5V FETs in the netgen setup file.
  Also: Corrected all of the contact and via drawing routines to get the proper overlap of each layer.
  
• posted: November 22, 2020 at 3:00am     version: 1.0     revision: 71
  Corrected the PDK units conversion, which was using floor() instead of round() and resulting in incorrect units. Corrected the sonos device, which was failing generation if the guard ring was not selected. Added options to all devices to generate vias on top of the contacts, since it is especially important in the SkyWater technology to get above the high-resistance local interconnect layer.
  Updated the version number and corrected a typo preventing vias from being generated on a guard ring's left side.
  Also: Corrected another minor error affecting the position of vias on the left and right sides of the guard rings.
  
• posted: November 21, 2020 at 3:00am     version: 1.0     revision: 70
  Corrected latchup DRC rules for nwells to include the special pnp layer for the pnp transistor base, so that it does not flag a false positive error.
  
• posted: November 20, 2020 at 3:00am     version: 1.0     revision: 69
  Corrected misspellings of device model names as pointed out by Matt Venn in issue #59 on github.
  Corrected misspellings of device model names as pointed out by Mitch Bailey in issue #59 on github.
  
• posted: November 19, 2020 at 3:00am     version: 1.0     revision: 68
  Reworked the THKOX (HVI) layer output generation rules; it now generally does the right thing, and flags problematic areas; a few such problematic areas are false positives.
  
• posted: November 18, 2020 at 3:00am     version: 1.0     revision: 67
  Change to the magic techfile to more properly handle the THKOX layer on GDS output; this removes some odd artifacts from the output, but there are still some issues (maybe only one?) that are still being debugged.
  retry on skywater-pdk conda-env fetch fail
  Also: add building the hvl library to the test cases
  Also: update skywater pdk commit hash
  Also: reduce the required size for passing
  Also: Updated version to go along with the pull request and other changes made locally.
  
• posted: November 17, 2020 at 3:00am     version: 1.0     revision: 66
  Changed the Makefile.in file so that it sets the "version" value in the Magic techfile to the result of "git describe --long", so that instead of updating the techfile version whenever I think about changing the revision value in the Makefile, it updates automatically.
  
• posted: November 16, 2020 at 3:00am     version: 1.0     revision: 65
  Modified the seal ring abstract view so that it shows as DRC clean under DRC style "drc(full)". Updated the magicrc file to default to MAGTYPE = "mag", as there are few reasons other than standard cell layouts to use "maglef" type.
  
• posted: November 15, 2020 at 3:00am     version: 1.0     revision: 64
  Corrected the other cifinput style (vendorimport) with the same additions for handling the special FET types in SRAM core cells as was done in the previous commit.
  
• posted: November 14, 2020 at 3:00am     version: 1.0     revision: 63
  Revised the rule for checking (effectively) HVI to nwell spacing. This must use a cif-drc rule because the chech needs to be to LV nwell, not HV nwell (which would have merged the HVI layer). Otherwise there are lots of false positive errors.
  Modified the definition of device ppu to include HVTP, as otherwise the SRAM core cell pFET gets interpreted as a pFET-HVT, which does not have the right model bins for the SRAM device.
  Also: Corrected the GDS read-in so that it correctly separates out the "npass" (smaller) device from the "npd" device.
  Also: Removed redundant extraction entries for two of the nFET devices (this change does not affect behavior in any way, as redundant entries are ignored).
  Also: Modified DRC rule for li to allow 45 degree angles inside the SRAM core cell. This is sort of a moot point, given all the ways normal DRC is violated inside the SRAM core, but whatever.
  
• posted: November 13, 2020 at 3:00am     version: 1.0     revision: 62
  Added a missing DRC rule for poly to HV-diffusion spacing.
  Added additional rules for HV nwell spacing, taps without contacts, and minimum tap area to satisfy the minimum PPLUS/NPLUS implant area rule.
  Also: Added additional rule for HVNTM spacing, especially for nhvnative transistors with a p-tap between them.
  Also: Moved two DRC-CIF rules out of the drc(fast) variant because that triggers all of the CIF layers to be generated and slows things way down.
  
• posted: November 12, 2020 at 3:00am     version: 1.0     revision: 61
  Modified foundry_install.py to add SPICE/CDL port index annotation to the generation of maglef files (which was done for layout views in mag/ but had been missed for layout views in maglef/). Also: Corrected a regexp for port labels that failed to match on labels with a sticky bit set, which was causing port numbering to get screwed up after being carefully set by the generation scripts. Thanks to Mitch Bailey for the fix.
  Updated the sky130/README file to include adding sky130_fd_io as a submodule, since that is now available in the skywater-pdk repository.
  Also: Corrected rules for poly spacing to poly resistor, which was causing false positive errors on mrp1 and pres resistors (the non-high-res resistors).
  Also: Corrected minor typo in the last commit.
  Also: And one more typo fixed.
  
• posted: November 9, 2020 at 3:00am     version: 1.0     revision: 60
  remove the script itself, since it's no longer needed
  Update openlane PDN config
  Also: Updated version to go alonge with the last two pull request merges.
  
• posted: November 8, 2020 at 3:00am     version: 1.0     revision: 59
  Corrected typos that crept into the MiM2 cap section after copy and paste from the MiM cap section, in the magic techfile.
  
• posted: November 7, 2020 at 3:00am     version: 1.0     revision: 58
  Removed the "cellname delete \(UNNAMED\)" commands from the generate_magic.tcl scripts, because this is causing a database corruption in magic. This is a "quick fix", as the nature of the database corruption needs to be investigated. This fix prevents apparently unrelated errors in the port indexing in the installed files in the library mag/ directories.
  
• posted: November 4, 2020 at 8:37pm     version: 1.0     revision: 57
  Changed seal ring generator to round up widths on layouts with odd-numbered lambda units; rounding down causes a tiny gap in the middle of the seal ring edges. Added angle restriction rules to the magic techfile.
  Corrected another couple of errors where EFS8A was referenced in the seal ring generator script instead of sky130A.
  Also: Removed the call to script fix_missing_diodes_lef.py, because the issues has purportedly now been fixed in the skywater-pdk repository.
  
• posted: November 4, 2020 at 3:00am     version: 1.0     revision: 56
  Corrected errors related to the standard cells and the DRC rules for several of the FET devices with HVT/LVT implants. Also corrected the missing extraction device for type "rmp", and removed unused options from the "device resistor" lines.
  Corrected a problem in the last commit in which an extra block of text in the magic techfile got accidentally copied and pasted.
  
• posted: November 3, 2020 at 3:00am     version: 1.0     revision: 55
  Changed the OSU library "rename" to include the (nonstandard) ".tlef" extension. Also, noting that the check for names after "rename=" that do not have file extensions is incomplete, added a case for "techlef" and a catch-all case at the end. This commit effectively implements Amr's pull request #46, but in a slightly different way.
  Updated VERSION to go along with the last commit.
  
• posted: October 30, 2020 at 3:00am     version: 1.0     revision: 54
  Finally corrected all of the eight diode types, which had a lot of typos left over from the conversion from s8 to sky130.
  Modified the OSU install so that sky130_osu_sc.tlef gets renamed to sky130_osu_sc_t18.tlef. This happens internally to foundry_install.py
  
• posted: October 29, 2020 at 3:00am     version: 1.0     revision: 53
  Added the npn_11v0 devices to the extraction types. Note that the 11V NPN looks like a mashup of an NPN and extended-drain FETs, and extracts that way, requiring a change to magic (not done yet) that can tell the extraction to ignore certain devices.
  Added handling of the 11V NPN and corrected for the problem of extracting the additional implicicit FET devices that are part of the NPN. This requires the latest version of magic (8.3.73) or else a device called "Ignore" shows up in the SPICE output.
  Also: Removed parameters from the ignored devices, as that is irrelevant additional information.
  Also: Replaced all the "s8" references in the custom seal ring generator scripts to "sky130".
  Also: Corrected the sky130.tech file for the required tap surrounding an LICON contact (which is zero on two sides); the rule for "diff" surround should be interpreted as meaning "diff" and not "tap".
  Also: Add openlane configs related to the I/O library
  Also: PAD GROUND -> PAD POWER
  Also: Corrected some errors in the diode parameterized cells that did not get cleanly converted from s8.
  
• posted: October 25, 2020 at 3:00am     version: 1.0     revision: 52
  Corrected outdated references to "s8" in the README.md file.
  Updated README.md with more complete instructions that will show up on the github page.
  
• posted: October 23, 2020 at 3:00am     version: 1.0     revision: 51
  base commit for travisCI auto testing
  Updated VERSION to go along with the travis-ci additions from the github pull request.
  
• posted: October 22, 2020 at 3:00am     version: 1.0     revision: 50
  fix the swapped lines in fix_missing_diodes_lef.py
  Updated VERSION along with the two pull request merges.
  Also: Fixed problem with regexp in the netgen setup not ignoring decap and fill cells for any library not having a 2-character designator after "sky130_fd_sc_", as pointed out by Mitch Bailey in issue 37.
  Also: Provisional additions of under-bump material and redistribution layer vias (testing whether these layers can be derived or need to be explicitly drawn).
  
• posted: October 21, 2020 at 3:00am     version: 1.0     revision: 49
  sky130: add support for sky130_osu_sc_t18
  Another few follow-up corrections.
  Also: Updating VERSION to go along with the git merge of the most recent OSU stuff.
  Also: openlane config updates (PR #30 and #31):
  Also: add WIRE_RC_LAYER to the common config.tcl
  Also: base commit for the lef modifying scripts
  Also: fixes
  Also: a lame solution to make sure you don't invalidate the lef (do the same thing twice)
  Also: cleanups and using hs/ms diodes in openlane
  Also: cleanup according to the reviews
  Also: Refer to the issue in a comment
  Also: Modified a number of scripts using "/bin/env" to make it "/usr/bin/env", since the "/bin" location does not exist on some versions of Linux.
  
• posted: October 18, 2020 at 3:00am     version: 1.0     revision: 48
  Corrections in the magic techfile for the PPLUS and NPLUS auto-generated layers, especially to avoid bridging across butted taps.
  Corrected and updated about half of the known missing/incorrect rules in the DRC ruleset.
  Also: Finished pass through the DRC rule templates and fixed all of them that I could determine how to fix, leaving only a handful of errors not handled correctly.
  
• posted: October 15, 2020 at 3:00am     version: 1.0     revision: 47
  Corrected the tab error in cdl2spi.py, and modified foundry_install.py to make use of LEF and "readspice" annotation when creating layout database files from GDS sources.
  Corrected the Magic device generator to paint nwell under pFETs when the guard ring is not selected (previously it was drawn with the guard ring so went missing when the guard ring was unselected). Corrected MiM cap DRC rules (to match the Calibre decks rather than the documentation, which has different layers for MiM cap). Note that Magic was modified to correct a wrong reported distance on CIF-DRC rules such as the one used for one of the MiM cap rules.
  
• posted: October 14, 2020 at 3:00am     version: 1.0     revision: 46
  Revised the install script for the released public repository for the I/O library sky130_fd_io. This mostly involved deleting files from the custom addition library, most of which need to be put back at some point with the new naming scheme.
  Filled in additional files for the sky130_ef_io overlays and additional cells.
  Also: Updated cdl2spi.py to handle resistors with models specified normally and not with $[...].
  
• posted: October 8, 2020 at 3:00am     version: 1.0     revision: 45
  Modified the cifinput section of the magic techfile to always draw pwell under p-tap (TAP AND-NOT NWELL). This serves to ensure that abstract views made with "lef write -toplayer" have the pwell masterslice layer to ensure the correct connectivity between the power and ground rails and the well and substrate, respectively.
  
• posted: October 3, 2020 at 3:00am     version: 1.0     revision: 44
  Corrected capacitor extraction (needed type "csubcircuit" and not "subcircuit" to get the correct L and W calculation).
  Corrected some errors in the netgen setup, including incorrect references to circuit1 vs. circuit2, and specifically ignoring the monte carlo parameters "nf" for transistors and "mf" for MiM capacitors.
  
• posted: October 1, 2020 at 3:00am     version: 1.0     revision: 43
  Moved sort_pdkfiles.py to common/, and modified behavior to always use the default sort (which is a natural sort), given that doing "glob.glob" on a file directory results in a pretty arbitrary and meaningless ordering.
  
• posted: September 26, 2020 at 3:00am     version: 1.0     revision: 42
  Added additional option "sort" to supply a sorting script to specify the order of files when compiled into a library; this allows the Makefile to enforce natural sort order and/or put dependent entries at the top. Also added a custom script for sky130 to handle the assortment of "include" statements in the standard cell verilog before generating the library files.
  openlane support for latch mapping in synthesis
  
• posted: September 25, 2020 at 3:00am     version: 1.0     revision: 41
  Various modifications to accommodate the somewhat complicated management of include statements in verilog files in order to build the compiled libraries.
  
• posted: September 23, 2020 at 3:00am     version: 1.0     revision: 40
  Modified the techfile to make use of a techfile extension added to magic that allows the paint/erase lines in "compose" to declare multiple types to be painted. This allows the "obslic" contact to be erased if painted over with obsm1 without erasing obsli underneath.
  One more addition to the magic techfile, to make metal1 electrically connected across obslic, which is only supposed to represent an obstruction on the lower (locali) layer.
  
• posted: September 22, 2020 at 3:00am     version: 1.0     revision: 39
  Added resistor type short as a custom modification to the device models. Changed "obslic" (li-m1 contact as an obstruction layer) to be defined not between obsli and obsm1, but between obsli and metal1. This is consistent with the use of obsli in the standard cells with the LEF files generated using the "-toplayer" option, and allows metal1 to be placed across the power rails and obslic contacts without generating DRC errors.
  Corrected the names of the mrdp_hv and mrdn_hv devices to match the sky130_fd_pr names, and made them resistor types rather than subcircuit types, to match the model definitions.
  
• posted: September 21, 2020 at 3:00am     version: 1.0     revision: 38
  First cut at properly incorporating the sky130_fd_pr primitive devices (much work do be done still).
  Updated VERSION along with sky130_fd_pr library changes
  Also: 2nd pass at updating the sky130 installer for sky130_fd_pr.
  Also: There are continued problems with simulating various devices, but the installation is generally correct.
  Also: Messed with the MiM cap definition before finally determining that the real problem is the same as the failure to compute W and L correctly for extended drain devices; i.e., the algorithm is wrong with the terminals are on a different plane.
  
• posted: September 18, 2020 at 3:00am     version: 1.0     revision: 37
  Corrected the DRC rule checking for metal1 hole area. It was not counting obstruction metal layers as part of the metal layers, and so was ending up flagging thousands of errors in the power rails of the standard cells, where the contacts (to li) were placed on obstruction layers as part of the "lef write -toplayer" option. This would only show up when using "drc(full)", which runs the minimum hole area check.
  
• posted: September 17, 2020 at 3:00am     version: 1.0     revision: 36
  Removed a lot of locks on layers, leaving mostly just obstruction and fill layers. Changed the names used for the DRC rules to match the names used in the Google/SkyWater online documentation.
  Corrected one typo in the techfile.
  Also: Corrected a typo in the magic techfile.
  
• posted: September 12, 2020 at 3:00am     version: 1.0     revision: 35
  Corrected the area parameter passed to the bipolar devices in the magic techfile, matching an update to magic to correct the area output for terminals other than the device identifier.
  
• posted: September 11, 2020 at 3:00am     version: 1.0     revision: 34
  Substantially revised the technology file for magic, the PDK device generator script for magic, the setup file for netgen, and the DRC torture test generator, to match the final naming conventions for the sky130_fd_pr library of primitive devices.
  
• posted: September 10, 2020 at 3:00am     version: 1.0     revision: 33
  Added support for the OSU standard cells for sky130 based on the existing repository.
  Modified the spectre_to_spice.py script to remove a specific use of "m" in expressions, which might be incorrect to begin with.
  Also: Added support for bipolar transistor types (using the pwell or nwell base layer as the transistor ID type) and bipolar transistor extraction.
  Also: Added preliminary support for extended drain devices (reading and extraction).
  Also: Finished implementing the three types of 20V extended drain devices (for reading and extracting; writing not yet supported).
  
• posted: August 31, 2020 at 3:00am     version: 1.0     revision: 32
  Split the cifinput section into two, because SkyWater sources have totally confused text and pin purposes in the GDS files, and need to have a style that maps both purposes onto "port".
  openlane configs updates
  Also: all common_pdn.tcl configs are now configurable
  Also: renamed variables to follow the conventions
  Also: Updated VERSION to go along with the last pull request.
  
• posted: August 29, 2020 at 3:00am     version: 1.0     revision: 31
  Additional changes/corrections to the spectre_to_spice script.
  
• posted: August 28, 2020 at 3:00am     version: 1.0     revision: 30
  More changes to the spectre_to_spice.py code.
  Added find_all_devices.py from the Google/SkyWater work, as it is a useful script for determining information about where a subcircuit can be found in a model directory hierarchy, although it is somewhat tied to the Google/SkyWater specific file hierarchy.
  
• posted: August 26, 2020 at 3:00am     version: 1.0     revision: 29
  Corrections, mostly to spectre_to_spice to handle various issues, especially with the use of primitive device prefixes 'C' and 'R' to call subcircuits.
  
• posted: August 20, 2020 at 3:00am     version: 1.0     revision: 28
  Added a new script "fix_subckt_params.py" which works with the spectre_to_spice.py script, and moves parameters from a .param block in a subcircuit up to the .subckt line, so that the parameter can be passed to the subcircuit.
  Added a script that parses a SPICE file and prints the parameters that are on the .subckt line, and the parameters that are internal to the subcircuit in a .param statement. Also, corrected spectre_to_spice.py to not add braces around an expression that is already encapsulated by single quotes, as that causes grief to ngspice.
  Also: Forced spectre_to_spice.py to translate spectre model types "resistor" and "r2" to SPICE semicondutor resistor model type "r". The former is almost certainly correct; the latter, I'm unsure of.
  
• posted: August 18, 2020 at 3:00am     version: 1.0     revision: 27
  Added "split_one_spice.py", a companion script to "spectre_to_spice.py" that splits up a SPICE file (output from "spectre_to_spice.py") that has multiple subcircuits in it into multiple files, one file per subcircuit. This is much like "split_spice.py" except that is does not try to break models out of subcircuits, and it is much more careful about placing global parameters with the subcircuits that use them, and finding global parameters and other parts of the file that are common to more than one of the subcircuits, and retaining them in the original file.
  
• posted: August 15, 2020 at 3:00am     version: 1.0     revision: 26
  Started the conversion of device model names to the new naming convention on the Google/SkyWater repository.
  
• posted: August 13, 2020 at 3:00am     version: 1.0     revision: 25
  Updated the magic techfile with the first draft of the completed automated waffle fill cif output style.
  
• posted: August 10, 2020 at 3:00am     version: 1.0     revision: 24
  Modified the magic device generator to properly handle the "nf" parameter on MOSFET devices when converting from a netlist to layout. Corrected the netgen setup to ignore both "nf" and "mult" as netlist parameters, as well as other non-critical parameters that may or may not appear in both the schematic and layout- extracted netlists.
  Corrections to the device generation script and magic techfile to support the specific-width xhrpoly and uhrpoly devices.
  Also: More corrections to spectre_to_spice.py and split_spice.py.
  Also: Made small whitespace fixes per contents of pull request #23 by Tim Ansell.
  
• posted: August 9, 2020 at 3:02am     version: 1.0     revision: 23
  Continuation operator needed in sky130/Makefile.in
  Seems that some changes (SRAM devices added to netgen setup)? were not committed previously?
  Also: Updated revision to trigger tarball and github mirror on new commits.
  
• posted: August 6, 2020 at 3:00am     version: 1.0     revision: 22
  Modified the configuration file to better handle the installation options. In particular, removed the "install-local" and "install-dist" targets in favor of just using "make install", with the install type dependent on the choices made by "configure". Made the local and distributed install paths specific to the PDK. Added the link type and efabless-style to the configuration options. Added a list of generic standard cell gates to be used by (not yet posted) software to automatically generate digital symbol libraries.
  Updated revision to force a new tarball and the github mirror.
  Also: Corrected the handling of parameters inside and outside a subcircuit call.
  
• posted: August 3, 2020 at 3:00am     version: 1.0     revision: 21
  OpenLane support for other sky130 variants
  Renamed some variables to more meaningful names
  Also: Minimal set up for autotools
  Also: Updated the README files to reflect the new use of the autoconf "configure" script, and updated the VERSION revision number.
  
• posted: August 2, 2020 at 3:00am     version: 1.0     revision: 20
  Changed "convert_spectre.py" to "spectre_to_spice.py". Corrected the script to properly identify weird "spectreisms" in which resistors or capacitors are prefixed as subcircuits with "x" but use a model which is a resistor or capacitor. Also: Added more handling of SRAM (coreid) layers in the magic techfile for support of OpenRAM, and added a first pass at fill pattern generation in magic.
  Additional fix to spectre_to_spice.py to handle spectreisms.
  Also: Updated revision to trigger new tarball and github mirror.
  
• posted: August 1, 2020 at 3:00am     version: 1.0     revision: 19
  Updated the magic techfile to correct a few errors and extend the support for SRAM cells (to read and extract; no attempt to try to write an SRAM cell correctly).
  
• posted: July 29, 2020 at 3:00am     version: 1.0     revision: 18
  Updated the convert_spectre.py script to correct a number of errors, especially related to CDL formats which may appear in spectre files. Added a "split_spice.py" script to take the output of "convert_spectre.py" and pull the subcircuit definitions out of it and put them in separate files.
  More fixes on the two spectre-to-SPICE conversion scripts.
  Also: Enabled the REDISTRIBUTION option in the Makefile for sky130A. Corrected the convert_spectre.py to ignore .scs files, which have no SPICE equivalent.
  
• posted: July 28, 2020 at 3:00am     version: 1.0     revision: 17
  Corrected the Makefile to correct the string used for excluding files from the LEF compile.
  Setting the default LINK_TARGETS to none
  Also: Minor typos fixed in the Makefile
  Also: Minor fixes to the magicrc and netgen setup files
  Also: Removing the :: from ::env because I normally don't like to force the scope of commands in Tcl, which causes problems if you try to rename the command. Although its use here is probably harmless, I find the notation cumbersome.
  Also: Removed ; after END LIBRARY
  Also: Added a comment about EF_STYLE in sky130/README
  Also: Commented out missing IO and OSU libraries
  Also: Using TECHNAME in klayout .lyt file
  
• posted: July 27, 2020 at 3:00am     version: 1.0     revision: 16
  Removed all of the routines that generate compiled libraries from individual files for various file formats (GDS, LEF, SPICE/CDL, and verilog (liberty is unfinished and probably never will be), and put the in individual files that can be either run separately from the command line or included into the foundry_install.py script and run internally.
  Additional corrections to the standalone library compile scripts.
  Also: Added the "END LIBRARY" line back to the end of the LEF library after removing all of the individual ones.
  
• posted: July 26, 2020 at 3:00am     version: 1.0     revision: 15
  Fix for naming conventions (only comments changed).
  
• posted: July 24, 2020 at 3:00am     version: 1.0     revision: 14
  Finished the first working draft of the spectre-to-SPICE conversion script.
  
• posted: July 23, 2020 at 3:00am     version: 1.0     revision: 13
  Added a convert_spectre.py script which makes a basic first-pass attempt to convert spectre files into valid SPICE files. Note that this does not attempt to guarantee ngspice compatibility, as that is handled by other scripts.
  
• posted: July 21, 2020 at 3:00am     version: 1.0     revision: 12
  Per the bug report by Ronan Barzic, corrected the staging_install.py script to correctly support LINK_TARGETS=none.
  
• posted: July 18, 2020 at 3:00am     version: 1.0     revision: 11
  Corrected the last commit where I accidentally inserted a tab, discovered by Sylvain Munaut (whose pull request I am improperly bypassing, sorry).
  
• posted: July 17, 2020 at 3:00am     version: 1.0     revision: 10
  Changed the "create_gds_library" command to use the new command option "gds library" in magic, so that the top level with the example cells is not saved into the GDS output (which can cause problems with some tools).
  
• posted: July 16, 2020 at 3:00am     version: 1.0     revision: 9
  Modified sky130.tech magic techfile to add nwell and pwell as masterslice layers to the LEF input setup; this should resolve issues with the VNB and VPB pins in standard cells. Along with that, committed a script to correct the layers assigned to VNB and VPB in the original sources.
  
• posted: July 15, 2020 at 3:00am     version: 1.0     revision: 8
  Corrected the Makefile, which was using the "exclude" option on the standard cell verilog that was supposed to be used on the standard cell LEF. Mostly all this does is to change the nature of the error that occurs. Ultimately the source of the LEF files needs to be fixed, which will happen eventually. Also corrected the generate() routine in soc_floorplanner. This fixes the behavior in which clicking on the "Generate" button in the floorplanner app causes an error.
  
• posted: July 14, 2020 at 3:00am     version: 1.0     revision: 7
  Corrected the surround rule for metal4 around via3 in the DRC and wiring sections. It had been implemented as 0.060 / 0.065 (directional) instead of 0.065 (regardless of direction).
  Removed the diode cell CDL files for sky130_fd_sc_hd, which are currently in the Google/SkyWater repository.
  
• posted: July 12, 2020 at 3:00am     version: 1.0     revision: 6
  Corrected sidewall values for poly through metal2, which had been missing from the original simulation.
  Updated README to correct the instructions for the Google/SkyWater repository install (had the wrong names for the library subdirectories).
  
• posted: July 11, 2020 at 3:00am     version: 1.0     revision: 5
  Corrected all of the parasitic capacitance values in the tables based on the values and equations in the SkyWater Calibre PEX decks, and verified by extracting an example with exhaustive combinations of overlapping poly, local interconnect, and metal layers.
  
• posted: July 9, 2020 at 3:00am     version: 1.0     revision: 4
  Minor corrections in the openlane configs
  Corrected the names of the various digital standard cell libraries in the README file (which had become scrambled).
  Also: Added Apache 2.0 license file.
  Also: Added additional license information to the README files.
  Also: Removed the custom technology LEF files, as these have been added to the Google/SkyWater git repository. Added more complete instructions for cloning and installing the Google/SkyWater repository. Modified the Makefile and qflow setup file for use with the technology LEF files from the repo.
  
• posted: July 8, 2020 at 3:00am     version: 1.0     revision: 3
  Reorganized the top level so that most working files for EDA tool setup are in directories with the EDA tool name. Updated the openlane setup files.
  Updated version to update website and the github mirror repository.
  Also: Added support for the OSU standard cell set for sky130, based on the existing repository.
  Also: Added back the qflow support for the OSU standard cell libraries.
  
• posted: July 7, 2020 at 3:00am     version: 1.0     revision: 2
  Added "distclean" target to the Makefile, which is expected by the scripts handling automatic updates to the tarball and website.
  Corrected variable reference in the README install instructions.
  
• posted: July 6, 2020 at 3:00am     version: 1.0     revision: 1
  Updated version to force an update on the system, and to force a mirror copy to github overnight.
  
• posted: July 5, 2020     version: 1.0     revision: 0
  First public release.

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Last updated: August 12, 2022 at 2:00am