[Eda-dev] routing wire widths

MannVLSI jmann at mannvlsi.com
Fri Oct 20 14:52:18 EDT 2017


 

I am trying to bring up Qflow on a vendor process that is 180 nm. I set up
my own bare-bones Magic technology file for the process since I only want to
do synthesis, place and route with Qflow and go back to working in my own
tool set. I have everything working except the wires used for routing are
only 3 lambda wide and in this process lambda is 0.01 um.

 

The vias and metal around the vias are all correct (28 x 28 lambda) but the
wires between vias are very thin. (see the attached screen shot.)

 

Where do the routing wire widths get set?

 

The .par files has entries for metal like:

    width M1 24

    width M2 28

    width M3 28

 

and the LEF file for the process has entries like:

LAYER M1

  TYPE ROUTING ;

  DIRECTION HORIZONTAL ;

  PITCH 0.56 0.56 ;

  WIDTH 0.24 ;

  OFFSET 0.28 0.28 ;

 

.

 

LAYER M2

  TYPE ROUTING ;

  DIRECTION VERTICAL ;

  PITCH 0.56 0.56 ;

  WIDTH 0.28 ;

 

Etc.

 

So I can't figure out where it is coming up with 0.03 um or 3 lambda.

 

Thanks,

 

Jim Mann

Mann VLSI Research LLC

 

 

I sent this a few days ago with an attachment. I figure it may have been
marked as spam so I'm resending it without the picture.

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