[Eda-dev] qflow Docker experiment

Øyvind Harboe oyvind.harboe at zylin.com
Fri Jul 5 16:28:12 EDT 2019


Yes, it gets past that stage now. Thanks!


   1. It now fails in qrouter. I suppose I may have to increase the DIEAREA
   or reduce the initial_density from 1. Using:  " initial_density=0.5 qflow
   build --tech gscl45nm ControlUnitTestBench". Hmm..... the right
   initial_density is going to vary wildly across the design. I've heard the
   words "routing by abutment" spoken by people who know what they are talking
   about w.r.t. custom silicon. Does this mean that the I route many
   "rectangles" of digital synthesis and then join them up with a bit of
   digital synthesis and global routing of the "rectangles" in the "routing
   channels" inbetween the pre-routed "rectangles"?
   2. There's a an assert: *rc2dly: malloc.c:2401: sysmalloc: Assertion *



>From top of ControlUnitTestBench.def:

VERSION 5.6 ;
DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;
DESIGN ControlUnitTestBench ;
UNITS DISTANCE MICRONS 2000 ;

DIEAREA ( -1900 -1900 ) ( 229520 164540 ) ;



$ qflow build --tech gscl45nm ControlUnitTestBench
[deleted]
Progress: Stage 2 total routes completed: 44042
Failed net routes: 3
*** Writing DEF file ControlUnitTestBench_route.def
Final: Failed net routes: 3
List of failed nets follows:
*** Writing RC file ControlUnitTestBench_route.rc
DEF2Verilog -v //ControlUnitTestBench.rtlnopwr.v -o
//ControlUnitTestBench_postroute.v
-p vdd -g gnd  -l  /usr/local/share/qflow/tech/gscl45nm/gscl45nm.lef
ControlUnitTestBench.def
Generating RTL verilog and SPICE netlist file in directory
   /
Running vlog2Verilog.
vlog2Verilog -c -v vdd -g gnd -o ControlUnitTestBench.rtl.anno.v
ControlUnitTestBench_postroute.v
vlog2Verilog -c -p -v vdd -g gnd -o ControlUnitTestBench.rtlnopwr.anno.v
ControlUnitTestBench_postroute.v
/usr/local/share/qflow/bin/vlog2Verilog -c -b -p -n -v vdd -g gnd -o
ControlUnitTestBench.rtlbb.anno.v ControlUnitTestBench_postroute.v
Running vlog2Spice.
vlog2Spice -i -l  /usr/local/share/qflow/tech/gscl45nm/gscl45nm.sp -o
ControlUnitTestBench.anno.spc ControlUnitTestBench.rtl.anno.v
Converting qrouter output to vesta delay format
Running rc2dly -r ControlUnitTestBench.rc -l
/usr/local/share/qflow/tech/gscl45nm/gscl45nm.lib -V
//ControlUnitTestBench.rtl.v
-d ControlUnitTestBench.dly
Reading Liberty timing file
/usr/local/share/qflow/tech/gscl45nm/gscl45nm.lib
Parsing library "gscl45nm"
End of library at line 6016
Lib Read:  Processed 6017 lines.

*rc2dly: malloc.c:2401: sysmalloc: Assertion `(old_top == initial_top (av)
&& old_size == 0) || ((unsigned long) (old_size) >= MINSIZE && prev_inuse
(old_top) && ((unsigned long) old_end & (pagesize - 1)) == 0)' failed.Abort
(core dumped)*
Converting qrouter output to SPEF delay format
Running rc2dly -D : -r ControlUnitTestBench.rc -l
/usr/local/share/qflow/tech/gscl45nm/gscl45nm.lib -V
//ControlUnitTestBench.rtl.v
-d ControlUnitTestBench.spef
Reading Liberty timing file
/usr/local/share/qflow/tech/gscl45nm/gscl45nm.lib
Parsing library "gscl45nm"
End of library at line 6016
Lib Read:  Processed 6017 lines.
rc2dly: malloc.c:2401: sysmalloc: Assertion `(old_top == initial_top (av)
&& old_size == 0) || ((unsigned long) (old_size) >= MINSIZE && prev_inuse
(old_top) && ((unsigned long) old_end & (pagesize - 1)) == 0)' failed.
Abort (core dumped)
Converting qrouter output to SDF delay format
Running rc2dly -r ControlUnitTestBench.rc -l
/usr/local/share/qflow/tech/gscl45nm/gscl45nm.lib -V
//ControlUnitTestBench.rtl.v
-d ControlUnitTestBench.sdf
Reading Liberty timing file
/usr/local/share/qflow/tech/gscl45nm/gscl45nm.lib
Parsing library "gscl45nm"
End of library at line 6016
Lib Read:  Processed 6017 lines.
rc2dly: malloc.c:2401: sysmalloc: Assertion `(old_top == initial_top (av)
&& old_size == 0) || ((unsigned long) (old_size) >= MINSIZE && prev_inuse
(old_top) && ((unsigned long) old_end & (pagesize - 1)) == 0)' failed.
Abort (core dumped)

Running vesta static timing analysis with back-annotated extracted wire
delays
vesta -c -d ControlUnitTestBench.dly --summary reports --long
ControlUnitTestBench.rtlnopwr.v
/usr/local/share/qflow/tech/gscl45nm/gscl45nm.lib

----------------------------------------------
Vesta static timing analysis tool
for qflow 1.4.31
(c) 2013-2018 Tim Edwards, Open Circuit Design
----------------------------------------------

Parsing library "gscl45nm"
End of library at line 6016
Lib read /usr/local/share/qflow/tech/gscl45nm/gscl45nm.lib:  Processed 6017
lines.
Parsing module "ControlUnitTestBench"
ERROR: Net
\controlUnit_io_configurationWordFetchControl_waitRequest_1341_/Y 0_000000
not found in hash table
Verilog netlist read:  Processed 19595 lines.

On Fri, Jul 5, 2019 at 5:04 PM Tim Edwards <tim at efabless.com> wrote:

> Hello Øyvind,
>
> > I believe FreePDK45 is used by the following commandline:
> >
> > qflow build --tech gscl45nm ControlUnitTestBench
> >
> > (ControlUnitTestBench.def emailed directly to you)
>
> Thank you for the example file.  I discovered the problem was a misplaced
> parenthesis causing an array bounds overflow in a string.  I fixed the
> problem in the git source.  You can pull the git master branch from
> opencircuitdesign.com now, or pull the qflow-1.4 branch tomorrow after
> it is updated, or fix the offending line in src/addspacers.c line 238,
> which should be:
>
>         definname = (char *)malloc(strlen(argv[optind]) + 5);
>
> That should fix the problem!
>                                         Regards,
>                                         Tim
>
> +--------------------------------+-------------------------------------+
> | R. Timothy Edwards (Tim)       | email: tim at efabless.com             |
> | efabless, inc.                 | web:   http://www.efabless.com      |
> | 2570 N. 1st St., Suite 200     | phone: (240) 489-3255               |
> | San Jose, CA 95131             | cell:  (408) 828-8212               |
> +--------------------------------+-------------------------------------+
>


-- 
Øyvind Harboe, General Manager, Zylin AS, +47 917 86 146
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