[Eda-dev] qflow Docker experiment

Tim Edwards tim at efabless.com
Fri Jul 5 16:56:00 EDT 2019


Hello Øyvind,

> Yes, it gets past that stage now. Thanks!
>
>  1. It now fails in qrouter. I suppose I may have to increase the DIEAREA
>     or reduce the initial_density from 1. Using:  " initial_density=0.5
>     qflow build --tech gscl45nm ControlUnitTestBench". Hmm..... the right
>     initial_density is going to vary wildly across the design. I've heard
>     the words "routing by abutment" spoken by people who know what they are
>     talking about w.r.t. custom silicon. Does this mean that the I route
>     many "rectangles" of digital synthesis and then join them up with a bit
>     of digital synthesis and global routing of the "rectangles" in the
>     "routing channels" inbetween the pre-routed "rectangles"?

 > Progress: Stage 2 total routes completed: 44042
 > Failed net routes: 3
 > *** Writing DEF file ControlUnitTestBench_route.def
 > Final: Failed net routes: 3
 > List of failed nets follows:

There were only three failing nets.  That means that either (1) you were
very unlucky in that the density is too high by just a tiny amount, or
(2) there is something about the placement that puts three of the nets
in some position it can't route to (this is of course not supposed to
happen but I would not necessarily rule it out).

You need to look at what the output says about the failed routes, then
look at them in the layout and see if there is something obviously wrong
about them, such as being a pin way up in a corner and boxed in by other
pins, or something like that.  If they are just three random internal
nets, then try setting the density a little lower, like 0.48.  It's even
possible that due to completely random factors, it might work at a
slightly higher density like 0.52.

>  2. There's a an assert: *rc2dly: malloc.c:2401: sysmalloc: Assertion *

I cannot tell anything from the assertion, but if like last time you
send me the set of files used, I can track down the bug.  The two files
(excluding the tech .lib file which I have) that I need are:

	layout/ControlUnitTestBench.rc
	synthesis/ControlUnitTestBench.rtl.v

					Regards,
					Tim

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