[Eda-dev] Experiment with gscl45nm with Verilog output from an LRU implemented in Chisel

Tim Edwards tim at efabless.com
Thu Jul 11 08:39:05 EDT 2019


Hello Øyvind,

> Did something change recently that improved fMax for the LRU case?

>         setup at destination = 7263.67

Again, the setup time of 7.2ns is completely off-base and suggests an
improper parsing of the FreePDK45 liberty file.  The liberty file syntax
is not so much a spec as it is an amalgam of numerous competing formats.
It is probably the worst file format invented since EDIF.

I am a bit backed up on things but I'll look into it.  I need to see if
there is a repeatable case.

Clearly the difference between the 1.9ns throughput of the gates and the
additional stated setup time of 7.2ns is the difference between running
at 526MHz vs. running at 110MHz.  The setup time is the full difference
between those two numbers.
					Regards,
					Tim

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