[Eda-dev] Line wrapping in netgen LVS reports?

Matthew Guthaus mrg at ucsc.edu
Tue Jul 16 13:34:49 EDT 2019


Hi Tim,

In the LVS reports, the columns are a fixed size. Sometimes this crops
potentially useful information. Is there a way to configure this? For
example, in the following, the second element attached to the net is not
fully shown on the left side.

Thanks,
Matt

NET mismatches: Class fragments follow (with fanout counts):
> Circuit 1: bank2_1rw_0w_0r_single          |Circuit 2:
> bank2_1rw_0w_0r_single
>
> ---------------------------------------------------------------------------------------
> Net: port_address_0_0/wl_15                |Net: wl0_15
>   replica_column_0/wl0_17 = 1              |  bitcell_array_0/wl0_15 = 1
>   bitcell_array_0/pbitcell_7/nmos_m1_w0_80 |  replica_column_0/wl0_17 = 1
>   dummy_array_1/wl0_17 = 2                 |  dummy_array_1/wl0_17 = 2
>   port_address_0/wl_15 = 1                 |  port_address_0/wl_15 = 1
>                                            |
> Net: port_address_0_0/wl_7                 |Net: wl0_7
>   replica_column_0/wl0_9 = 1               |  bitcell_array_0/wl0_7 = 1
>   bitcell_array_0/pbitcell_71/nmos_m1_w0_8 |  replica_column_0/wl0_9 = 1
>   dummy_array_1/wl0_9 = 2                  |  dummy_array_1/wl0_9 = 2
>   port_address_0/wl_7 = 1                  |  port_address_0/wl_7 = 1
>
> ---------------------------------------------------------------------------------------
> Netlists do not match.
> Netlists do not match.


-- 
Matthew Guthaus
Professor, Computer Science & Engineering
University of California Santa Cruz
https://www.soe.ucsc.edu/people/mrg
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