Qflow 1.1

Table of Contents

Revision information on Qflow version 1.2
Revision information on Qflow version 1.1
Revision information on Qflow version 1.0
Revision information on Qflow version 0.9

Revision information on Qflow version 1.2 (Development):

Revision information on Qflow version 1.1 (Stable):

Revision information on Qflow version 1.0:

  1. April 9, 2013
    Qflow converted from a loose set of independent scripts into a package with an install location. Scripts greatly revised and extended to fit the new package format. All scripts extended to use the OSU 0.35um open-source standard cell set by default. Capability to split nets with large fanout into trees added.
  2. April 9, 2013 at 5:09pm
    Third time's the charm.
    Also: Update at Tue Apr 9 17:08:54 EDT 2013 by tim
    Also: Merge branch 'master' into work
  3. April 10, 2013 at 3:00am
    Various updates, corrections to make the example circuit complete the entire flow without errors. Much more to do, but it's a good start.
    Also: Update at Tue Apr 9 19:58:56 EDT 2013 by tim
    Also: Merge branch 'master' into work
  4. April 11, 2013 at 3:00am
    Added a few scripts for file conversion. These are not yet part of the official flow.
    Also: Update at Wed Apr 10 11:44:01 EDT 2013 by tim
    Also: Merge branch 'master' into work
  5. April 12, 2013 at 3:00am
    Trivial changes. . .
    Also: Update at Thu Apr 11 10:39:20 EDT 2013 by tim
    Also: Merge branch 'master' into work
  6. April 13, 2013 at 3:00am
    Implemented a technology-independent spacer (filler cell) adding routine "addspacers.tcl".
    Also: Update at Fri Apr 12 14:04:55 EDT 2013 by tim
    Also: Merge branch 'master' into work
    Also: Forgot to map the output of addspacers back to the original filename so that the correct file will be used by the router.
    Also: Small modification to add output to the log file instead of dumping it to the terminal.
  7. April 15, 2013 at 3:00am
    Changed sis input from "rlib" to "read_library", as "rlib" became deprecated at some point, but sis versions from 1.3 should understand the "read_library" command.
    Also: Update at Sun Apr 14 19:20:53 EDT 2013 by tim
    Also: Merge branch 'master' into work
  8. May 1, 2013 at 3:00am
    Corrected an error in the configure script that would prevent setting libdir and other paths to anything other than the default.
    Also: Update at Tue Apr 30 17:52:27 EDT 2013 by tim
    Also: Merge branch 'master' into work
  9. May 9, 2013 at 3:00am
    A number of changes. Most changes involve support of power and ground connections; e.g., unused set or reset pins on flops. Normally direct connections to power and ground are optimized out of verilog logic, but this does not apply to cells added during post-processing. In particular, where a set or reset flop is needed but only a set+reset flop is available, one input will have to be tied. Additional code supports both positive and negative reset inputs to flops. Yet more code cleans up a few places where gate pin names were hard-coded into the scripts. Finally, the technology parameters have been removed from the "qflow_vars.sh" file, as they are technology-dependent but not project-dependent. The end-user should not be modifying these values.
    Also: Update at Wed May 8 19:48:28 EDT 2013 by tim
    Also: Merge branch 'master' into work
  10. May 10, 2013 at 3:00am
    Corrected a minor error preventing BDnetFanout from running.
    Also: Update at Thu May 9 14:08:19 EDT 2013 by tim
    Also: Merge branch 'master' into work
    Also: Corrected the BDnetFanout source as well so that a missing "ignore" file will not crash the program. Also made sure "ignore" file is properly closed after reading.
    Also: Put the call to BDnet2BSpice back in the synthesis and resynthesis scripts, to create the netlist-derived SPICE netlist needed for LVS.
  11. May 11, 2013 at 3:00am
    Made modifications to BDnet2BSpice to take as an input argument the filename of a SPICE library of subcircuits representing the standard cells. This allows BDnet2BSpice to match the port order of the standard cells, as the BDNET netlist cannot be assumed to have the same port order (especially as the BDNET format does not even refer to the power connections). Also added handling of arguments passed for the name of the power and ground nets. Added the SPICE file for the osu035 technology to the example technology database in qflow, and modified the synthesis scripts to use the new syntax for BDnet2BSpice.
    Also: Update at Fri May 10 13:33:32 EDT 2013 by tim
    Also: Merge branch 'master' into work
    Also: Corrected an error in the core bounding box position calculated by place2def2.tcl, which was causing the tool to sometimes generate obstruction regions over part of the core. When gate pins were far enough to the right to be under that obstruction, qrouter could no longer route to them.
  12. May 12, 2013 at 3:00am
    Corrected the unused input to a DFFSR when used as a set-only or reset-only flop, when the set and/or reset pins are inverted.
    Also: Update at Sat May 11 09:22:40 EDT 2013 by tim
    Also: Merge branch 'master' into work
    Also: Expanded the verilog preprocessor to handle "parameter" statements, which VIS does not.
  13. May 14, 2013 at 3:00am
    Small modification to vpreproc (nonfunctional)
    Also: Update at Mon May 13 11:26:32 EDT 2013 by tim
    Also: Merge branch 'master' into work
  14. May 17, 2013 at 3:00am
    Modified qflow to add the magic startup script to the layout directory, and to substitute the path to the techfile into the startup script in the install directory.
    Also: Update at Thu May 16 10:34:43 EDT 2013 by tim
    Also: Merge branch 'master' into work
  15. July 15, 2013 at 3:00am
    Accidental commit of object files and other temporary build files. Will be removed.
    Also: Update at Sun Jul 14 15:34:16 EDT 2013 by tim
    Also: Merge branch 'master' into work
    Also: Removed temporary build files from the distribution.
  16. July 16, 2013 at 3:00am
    Corrected an error which was setting the current working directory name to lowercase when generating paths, causing errors with directory names having capital letters in them.
    Also: Update at Mon Jul 15 15:12:58 EDT 2013 by tim
    Also: Merge branch 'master' into work
  17. July 18, 2013 at 3:00am
    Changed the flow so that "placement.sh" is always run with the "-d" option. This is unnecessary if the fanout buffer stage is run, but one cannot assume that the end-user will choose to run the fanout buffering, and so the placement stage should ALWAYS prepare all the files needed by the router.
    Also: Update at Wed Jul 17 09:05:24 EDT 2013 by tim
    Also: Merge branch 'master' into work
    Also: Made changes to "vpreproc.c" to ignore "always" blocks that either contain no references to a clock, no references to a reset signal, or both. Also modified the code to handle "always" blocks that contain a single "if" statement and therefore do not have "begin" and "end" statements. All of this just highlights the relative insanity of verilog syntax. . .
    Also: Quick correction to the last commit.
    Also: Added preliminary support for the Odin-II verilog parser.
  18. July 19, 2013 at 3:00am
    Corrections to the preprocessor for VIS, to remove ending semicolon from parameters, and to remove comma characters from register names where there are more than one register name per line.
    Also: Update at Thu Jul 18 11:16:04 EDT 2013 by tim
    Also: Merge branch 'master' into work
    Also: Some extensions to the preprocessor, restoring the ability of the former preprocessor script to handle vector subranges on the right-hand-side. Also, fixed some of the block parsing for multiple clock domains, in preparation for actually handling the multiple clock domains.
  19. July 22, 2013 at 3:00am
    Correction to vpreproc.c, which was closing the input file before writing the "endmodule" line. At best, this causes immediate errors with the downstream verilog parser.
    Also: Update at Sun Jul 21 13:42:37 EDT 2013 by tim
    Also: Merge branch 'master' into work
  20. July 26, 2013 at 3:00am
    This is a major update to qflow, replacing the tools "VIS" and "SIS" with "odin_II" and "abc", respectively. The flow can now handle multiple clock domains and a respectably large variety of verilog syntax.
    Also: Update at Thu Jul 25 13:24:13 EDT 2013 by tim
    Also: Merge branch 'master' into work
  21. July 27, 2013 at 3:00am
    Update to vpreproc, still trying to accomodate a whole bunch of random variations people use for verilog syntax.
    Also: Update at Fri Jul 26 14:47:22 EDT 2013 by tim
    Also: Merge branch 'master' into work
  22. July 30, 2013 at 3:00am
    Added the OSU 0.5um standard cell set, with a lot of help from Rodolfo del Valle (thanks!).
    Also: Update at Mon Jul 29 18:33:01 EDT 2013 by tim
    Also: Merge branch 'master' into work
  23. July 31, 2013 at 3:00am
    Modifications to the OSU 0.5um technology files to correct errors and add missing components needed by qflow.
    Also: Update at Tue Jul 30 10:12:11 EDT 2013 by tim
    Also: Merge branch 'master' into work
    Also: One additional modification moves one of the VDD fingers in DFFSR from being marked as an obstruction, to the VDD pin geometry. Technically, ALL of these bits of geometry should be part of the pin geometry, and not part of the obstruction. However, this particular one interferes with qflow by making qrouter believe that VDD is "boxed in" by obstructions, and prevents it from routing static VDD connections from pins to the power bus. Note, however, that one is supposed to connect signals that are tied permanently high or low to a "tiehi" or "tielo" cell, which has a small resistor between the internal connection and the power bus, and prevents potential ESD issues from having a small digital gate connected directly to a chip pin. The real issue is that there are no "tiehi" or "tielo" cells in the OSU standard cell set, and the existing problem only arises as a result of trying to hack in a direct connection to the power bus in order to make the layout match the netlist.
    Also: Additional correction to the IRSIM parameter file for OSU050
    Also: Update to the configure script and makefiles to correctly support the use of --with-libdir= and --with-bindir= to allow an installation in a non-default location.
  24. August 3, 2013 at 3:00am
    Modified the synthesis script to make use of newest Odin-II code, which avoids the need for a custom patch, and also allows latches to be set to 0 in the .blif file to prevent making abc unhappy. Thanks to Ken Kent for the Odin-II updates!
    Also: Update at Fri Aug 2 20:05:40 EDT 2013 by tim
    Also: Merge branch 'master' into work
  25. August 16, 2013 at 3:00am
    Update to vpreproc tool to (1) correctly handle parameters with spaces in the parameter definition, (2) correctly handle parameters with nested parameters in the definition, and (3) handle vector bundles in the assignment of reset values.
    Also: Update at Thu Aug 15 08:41:01 EDT 2013 by tim
    Also: Merge branch 'master' into work
  26. August 17, 2013 at 3:00am
    Correction to a major error that cropped up with the last update to Odin_II and ABC. ABC, unlike sis, buffers the outputs, so it becomes incorrect to remove the trailing _FF_NODE added by Odin_II to buffer outputs. Instead, only those DFF outputs that are not module outputs should have _FF_NODE removed, so that simulators can see the original signal names, and the rest should be left untouched. The synthesis flow is simplified by not requiring the use of AddIO2BDnet, although there need to be some hooks to user-space to allow AddIO2BDnet to latch asynchronous inputs or double-buffer outputs.
    Also: Update at Fri Aug 16 09:53:46 EDT 2013 by tim
    Also: Merge branch 'master' into work
    Also: Corrected an error in vpreproc that would overwrite the reset signal name if the reset was followed immediately by space and the close-parenthesis for the always() statement.
  27. August 18, 2013 at 3:00am
    Corrected the so-called "resynthesis" script (clock tree generator), which was still referring to "_buf" names and therefore basically failed to run. Increased the number of I/Os handled by the BDnet2BSpice and BDnet2Verilog tools, although this is a poor substitute for dynamic allocation.
    Also: Update at Sat Aug 17 11:15:19 EDT 2013 by tim
    Also: Merge branch 'master' into work
  28. August 21, 2013 at 3:00am
    Rewrote the clocktree algorithm to limit the number of branches in any one tree to the maximum allowed fanout. This also corrects an error in which some branches of a fanout tree could be driving no gates at all. There was also a minor error causing some buffer outputs to be printed twice in the node list; this has been fixed.
    Also: Update at Tue Aug 20 17:50:01 EDT 2013 by tim
    Also: Merge branch 'master' into work
    Also: Added handling of LOGIC0 and LOGIC1 generic gates for technologies whose standard cell set does not include tie-high and tie-low cells.
  29. August 22, 2013 at 3:00am
    Corrected an error in the cleanup script that was still referring to a filename with "_buf".
    Also: Update at Wed Aug 21 11:43:57 EDT 2013 by tim
    Also: Merge branch 'master' into work
    Also: Corrected a minor typo in place2def2.tcl, which was calling itself place2def.tcl.
    Also: Implemented what are hopefully some halfway rational ways to deal with the output. Most extraneous output ends up in "synth.log". Information about what's running at what time is also dumped to the screen. Qrouter, because it can take so long to run, is teed to both synth.log and into a grep function that looks for major errors/failures but also ticks out statements every 100 routes so that the user doesn't start thinking that something has gone bye-bye.
  30. August 23, 2013 at 3:00am
    Additional work to capture errors. Within a specific qflow master script, each step is checked for one output file that it is supposed to create. If the file does not exist or is older than some key file generated earlier in the same qflow run, then the script stops and exits with an error. Note that this does not capture errors between scripts in qflow_exec.sh, yet.
    Also: Update at Thu Aug 22 09:06:28 EDT 2013 by tim
    Also: Merge branch 'master' into work
    Also: Added options "build" and "all" to "qflow", so that qflow can be run from the command line without remembering all the steps to write in.
  31. August 26, 2013 at 3:00am
    Corrected an error preventing use of a locally defined tech directory.
    Also: Update at Sun Aug 25 09:48:02 EDT 2013 by tim
    Also: Merge branch 'master' into work
    Also: Corrected the synthesis script to avoid an undefined variable error if BDnetFanout is not run due to lack of support in the technology files.
  32. August 31, 2013 at 3:00am
    Corrected an error in clocktree where an empty cluster can cause a divide-by-zero.
    Also: Update at Fri Aug 30 20:16:49 EDT 2013 by tim
    Also: Merge branch 'master' into work
  33. September 2, 2013 at 3:00am
    Created a new tool called "liberty2tech", that is useful for generating a flow for a new technology. It will parse a standard "Liberty" format timing file, and generate a genlib file for ABC for standard-cell mapping, and a "gate.cfg" file for BDnetFanout for load balancing. Those are the most difficult files to create for the flow.
    Also: Update at Sun Sep 1 19:55:46 EDT 2013 by tim
    Also: Merge branch 'master' into work
  34. September 3, 2013 at 3:00am
    Added liberty2tech compile/install to Makefile.in
    Also: Update at Mon Sep 2 08:27:12 EDT 2013 by tim
    Also: Merge branch 'master' into work
    Also: Modified liberty2tech to use a simple pattern matching to determing which cells get put in the genlib file.
    Also: Made some changes to avoid having scripts hard-code the DFF clock and input pins. Instead, these pin names are specified in the technology .sh script.
    Also: Corrected an error preventing the use of set and reset flops.
    Also: Corrected an error allowing long input/output lists to overrun memory in BDnetFanout.
    Also: Modified the techfiles distributed with the OSU035 and OSU050 technologies to use the better "device" extraction models instead of the old "fet" models. This also allows the default substrate node name to be set by the Tcl variable GND, instead of being hardwired into the techfile.
  35. September 4, 2013 at 3:00am
    Added features to liberty2tech to deal with local overrides of template index values, and to handle various differences between the format of the function string. This includes handling implicit ANDs (e.g, "A B") and XOR using "^".
    Also: Update at Tue Sep 3 11:42:17 EDT 2013 by tim
    Also: Merge branch 'master' into work
    Also: Expanded liberty2tech to handle templates in either orientation, and to expand the index and value strings into numerical arrays for easier processing at the end (and for future, more complicated processing).
    Also: Updated the genlib and gate.cfg files for osu035 and osu050 from the liberty format files that come with the standard cell distributions.
    Also: And additional expansion of the function strings handled by liberty2tech, to accept a single-quote after a pin name or a nested expression, as equivalent to "!" before the pin name or expression (that is, inversion in postfix notation rather than prefix notation). This is specifically to support the pharosc cells from vlsitechnology.org. Also, fixed the tokenizer to remove trailing whitespace.
  36. September 7, 2013 at 3:00am
    Qflow corrections: postproc.tcl will not skip parsing a file if nothing is in the .init file: It still needs to replace the default flop names with the general-purpose flop cell for the technology! Also: Checked in new verilog preprocessor "verilogpp", which is a huge improvement over "vpreproc". However, it is not yet used by the synthesis script; awaiting more testing.
    Also: Update at Fri Sep 6 20:22:01 EDT 2013 by tim
    Also: Merge branch 'master' into work
  37. September 8, 2013 at 3:00am
    Replaced the vpreproc tool with the new verilogpp tool. This not only is better at correctly interpreting procedural blocks in verilog. It also handles `ifdef statements, includes files that are specified by `include, and makes a number of replacements of syntax that is not handled by Odin_ii. It also handles instance calls, where the instance names found in a source file are dumped to a dependency list in a file called ".dep". Changes to the synthesis script parse the .dep file and recursively call the preprocessor on the dependent files, and their dependent files, and so on. All files needed to be read by Odin_ii are dumped into an XML configuration file that Odin_ii knows how to read.
    Also: Update at Sat Sep 7 14:06:39 EDT 2013 by tim
    Also: Merge branch 'master' into work
    Also: One additional correction to send stderr output from abc to the log file; otherwise, program crashes cannot be caught.
    Also: Using the new "-k" switch on qrouter; some changes to the osu050 tech to see what affect it has on the behavior of ABC. Apparently none. . .
    Also: Correction to BDnetFanout, to avoid overwriting the string-terminating NULL when shifting characters to make room for a gate name that is longer than the original.
    Also: Slight change to the last modification, nothing important. . .
    Also: Removed error message reporting from "qrouter -i", because it appears to always be generating an error return code, for some reason.
  38. September 9, 2013 at 3:00am
    Corrected a fairly major error (only off by a factor of 1000!) in which the gate.cfg files for osu035 and osu050 had delay/cap in units of fs/fF, which was read by BDnetFanout as ps/fF. The liberty2tech tool was the root cause of the error. Also cleaned up some incorrect printf statements in BDnetFanout, and removed the "-k" switch for qrouter, which was experimental (and breaks when used with earlier versions of qrouter).
    Also: Update at Sun Sep 8 08:49:15 EDT 2013 by tim
    Also: Merge branch 'master' into work
    Also: Added to qflow the ability to add padding area to the layout with fill cells, using a user-supplied percentage fill amount. To go along with this, added the "project_vars.sh" file to the list of files generated by qflow to go in the project top-level directory. As of now, the user-supplied percentage fill is the only value used in that file, but this will be greatly expanded upon in the near future.
    Also: Corrected an unbalanced parenthesis introduced into the osu050.genlib tech file.
  39. September 10, 2013 at 3:00am
    Changed the handling of fill cells completely. To get a better result from TimberWolf, each cell is now given implicit feedthrough tracks across the cell. This causes the global router to produce a solution that is much closer to a sea-of-gates router result. Instead of removing explicit feedthroughs placed by TimberWolf, the explicit feedthroughs are turned into fill cells, and retained in the layout. All of this helps to avoid routing congestion and improves the chance of getting a valid routing result.
    Also: Update at Mon Sep 9 09:29:26 EDT 2013 by tim
    Also: Merge branch 'master' into work
    Also: Correction to the ".par" parameter files used by TimberWolf for the two supported technologies. Specifically, correct values were entered for layer resistance and capacitance, correct values for layer width, and layer spacing was adjusted relative to layer width to provide the correct routing track spacing using the formula (track separation = metal width + metal spacing).
    Also: One further small correction to a comment line with incorrect information.
    Also: And a few more small things. . . added 'random.seed' to the .par file so that runs will be repeatable, and rewrote the grep function for tracking qrouter output so that it only prints every 100 commits, not when the commit is, say, 4004.
    Also: Correction to the last update to place2def.
  40. September 12, 2013 at 3:00am
    Found that TimberWolf can violate track pitch when placing pins, so it is possible for pins to overlap by occupying the same grid point. Changed place2def.tcl to prevent this from happening. Also, changed the "qflow" script to handle creating the initial ".par" file in the layout directory, instead of the synthesize script. qflow now checks both the ".par" and ".magicrc" files, and in the case of a technology file update or a technology change for the project, will copy the existing file to a backup name, and generate the new file. This will avoid all sorts of weird problems caused by switching to a different technology while having a conflicting .par file or .magicrc file.
    Also: Update at Wed Sep 11 12:19:30 EDT 2013 by tim
    Also: Merge branch 'master' into work
    Also: Modified clocktree to pick up the random seed number (if any) that is in the .par file. Otherwise, clocktree's manipulations will invalidate the reproducibility of results from the other tools (namely TimberWolf, the only other one to use randomization). With this fix, results ARE repeatable from run to run, given the same source file and parameters.
    Also: Corrected liberty2tech (once again), where a correction to the slope was not applied to all its dependent calculations. The genlib format was changed from ps to ns, as per genlib documentation, although I don't think the abc calculation are dependent on the absolute value. Still, better to stick with the documentation, to avoid confusion.
  41. September 13, 2013 at 3:00am
    Allows the technology script to set variable "resolution", which is passed on to qrouter as the "-r " option, and lets qrouter handle things on the nanometer scale, if necessary. Not used by distributed technologies osu035 and osu050.
    Also: Update at Thu Sep 12 13:54:20 EDT 2013 by tim
    Also: Merge branch 'master' into work
    Also: Corrected two fprintf lines in verilogpp error messages. Fixed a bdnet2cel round-off error in calculating the cell height and width of macros read from the LEF file.
  42. September 14, 2013 at 3:00am
    Modified the qflow "configure" script to allow the use of the much simpler "--with-vtr=<DIR>" in place of the separate --with-Odin_II= and --with-abc=, when both programs (or either program) comes as part of the VTR package. The original switches are still valid.
    Also: Update at Fri Sep 13 10:42:08 EDT 2013 by tim
    Also: Merge branch 'master' into work
  43. September 15, 2013 at 3:00am
    Added some option handling. The "project_vars.sh" file is now a place where one can specify options for different tools in the chain. The options can also be set by the technology script, which is parsed first, and overridden from "project_vars.sh", in case a specific technology has a need to specify a certain command-line option for one or more of the tools in the chain. This does not yet deal with all the options that go to the various Timberwolf tools, which are their own headache.
    Also: Update at Sat Sep 14 17:11:58 EDT 2013 by tim
    Also: Merge branch 'master' into work
    Also: Another change: technology is now picked up from the existing "qflow_vars.sh" file if "qflow" is being run again in the same project directory, which avoids the sort of catastrophic consequence of failing to specify "--tech" just to refresh, or just to run again off of the command line.
  44. September 16, 2013 at 3:00am
    Removed the hard-coded via stack specifier, and made it settable from the tech or user script. Added a search for a ".cfg2" file that can be appended to the ".cfg" file to add additional information for qrouter.
    Also: Update at Sun Sep 15 10:22:17 EDT 2013 by tim
    Also: Merge branch 'master' into work
    Also: Correction to qflow.sh.in to avoid printing messages about values used for "tech" before the command line has been parsed for a --tech switch.
    Also: Corrected a typo. . .
    Also: Another slight change, to move some manipulations of the .cfg file out of place2def.tcl and into placement.sh.
    Also: One last correction to syntax. . .
    Also: A vague attempt to parse and modify verilog statements of the form "wire <name> = <value>", which Odin_II does not like. The procedure is to break the line into two lines, "wire <name>;" and "assign <name> = <value>".
  45. September 24, 2013 at 3:00am
    Update at Mon Sep 23 22:18:33 EDT 2013 by tim
  46. October 1, 2013 at 3:00am
    Modified .gitignore for project
    Also: Merge branch 'master' into work
    Also: Added an important initialization to the state stack pointer that will otherwise cause a crash on systems that don't zero pointers on allocation.
    Also: Update at Mon Sep 30 11:47:18 EDT 2013 by tim
    Also: Merge branch 'master' into work
  47. October 3, 2013 at 3:00am
    Preprocessor correction when popping out of the last "end" statement for an "always" block. I am concerned that there is a counterexample to this. . .
    Also: Update at Wed Oct 2 10:12:31 EDT 2013 by tim
    Also: Merge branch 'master' into work
    Also: Corrected the verilogpp source in the correct way, this time.
  48. October 4, 2013 at 3:00am
    Correction to verilogpp.c covering a case where a negative edge reset was not printed to the .init file, causing a cascade of errors downstream.
    Also: Update at Thu Oct 3 11:30:57 EDT 2013 by tim
    Also: Merge branch 'master' into work
  49. October 5, 2013 at 3:00am
    Added code needed to handle resets that are declared to be internal assigned wires. Very similar handling to the clocks that are assigned internal wires. The name of the reset signal is modified to ensure it can be found by the postprocessing step, then added to the modules output signal list. This keeps the synthesis tool from optimizing it out of existance. After synthesis, it is removed from the output list and given its original name. The remainder of the reset signal handling for resetting flip-flops is the same as before.
    Also: Update at Fri Oct 4 17:38:59 EDT 2013 by tim
    Also: Merge branch 'master' into work
  50. October 9, 2013 at 3:00am
    Some modifications to avoid redundant handling of clocks and reset signals by vmunge; correction of verilogpp to clear out tentative subcircuits that were found not to be.
    Also: Update at Tue Oct 8 11:28:23 EDT 2013 by tim
    Also: Merge branch 'master' into work
  51. October 10, 2013 at 3:00am
    Overhaul of qflow to eliminate all uses of the "BDNET" format in favor of the (slightly less obscure) BLIF netlist format. A few scripts that are not part of the main flow (bdnet2sim and rtl2bdnet) have not yet been modified for handling BLIF files. Also, corrected an error in BDnetFanout (now blifFanout) in which a change in units caused a maximum value setting to be in a typical range, causing odd error messages about gate strengths being too low.
    Also: Update at Wed Oct 9 12:02:14 EDT 2013 by tim
    Also: Merge branch 'master' into work
  52. October 11, 2013 at 3:00am
    Rewrote the verilog preprocessing and postprocessing routines to properly record module hierarchies, and track signals, clocks, and resets through the hierarchy when replacing "latch" statements with reset flops.
    Also: Update at Thu Oct 10 10:28:15 EDT 2013 by tim
    Also: Merge branch 'master' into work
  53. October 12, 2013 at 3:00am
    Some more modifications to the new routines, and a correction to vmunge.tcl when replacing clock and reset signals with loopback versions.
    Also: Update at Fri Oct 11 09:41:14 EDT 2013 by tim
    Also: Merge branch 'master' into work
    Also: Found that the substitutions previously done by blifrtl2bdnet were missing, now that BDNET files are no longer used and blifrtl2bdnet has been removed from the flow. Recast the substitutions into sed scripts and put into synthesize.sh.
    Also: Further refinement of XML file generation for Odin-II to avoid repeating files that are called multiple times from different sources.
  54. October 20, 2013 at 3:00am
    A few corrections to (1) verilogpp.c for parsing "always @(*)" syntax, and (2) liberty2tech.c, to actually read the statements declaring the time and capacitance units used in the file, and to handle all the units accordingly; (3) the gate.cfg files for osu035 and osu050 to correct for errors caused by the previously incorrect liberty2tech, and (4) additions to most of the scripts and tools to use yosys as an alternative synthesis frontend. For now, qflow is not making optimal use of yosys, but will be upgraded soon. Documentation will follow, shortly.
    Also: Update at Sat Oct 19 10:49:15 EDT 2013 by tim
    Also: Merge branch 'master' into work
  55. October 25, 2013 at 3:00am
    Major update to support yosys, following changes made to yosys by Clifford Wolf to support set-reset flops, making yosys useable with the OSU035 standard cell set. Modified a large number of script files to support yosys as the primary synthesis frontend, while keeping Odin_II as an alternative synthesis frontend. Since yosys could synthesize the openMSP430 microcontroller, this forced me to rewrite the old and horrible parsing code in blif2BSpice and blif2Verilog to make better use of allocated memory instead of fixed-size character arrays. Documentation on the opencircuitdesign website will follow shortly.
    Also: Update at Thu Oct 24 19:47:28 EDT 2013 by tim
    Also: Merge branch 'master' into work
  56. October 26, 2013 at 3:00am
    Added script "ybuffer" to add buffers between internal signals and the module output, which is what "AddIO2BDnet" used to do, and what Odin_II does automatically.
    Also: Update at Fri Oct 25 13:35:25 EDT 2013 by tim
    Also: Merge branch 'master' into work
  57. October 30, 2013 at 3:00am
    Update with a reasonably good, working version of the vesta static timing analysis tool.
    Also: Update at Tue Oct 29 20:16:05 EDT 2013 by tim
    Also: Merge branch 'master' into work
  58. October 31, 2013 at 3:00am
    Added setup time calculation at path termination on a flop input. Added path loop identification. Made a few optimizations for speeing up program execution. Worst case can still be very bad, though, for long combinatorial chains with a lot of fanout points.
    Also: Update at Wed Oct 30 17:51:18 EDT 2013 by tim
    Also: Merge branch 'master' into work
  59. November 1, 2013 at 3:00am
    Modifed the STA to use a "--fastmode" that does not attempt to find the worst-case timing, but gets close, and does not get stuck in deep combinatorial hierarchies. The scripts have been updated to use the fast mode, as well as taking user-supplied options from the qflow_vars.sh script. Vesta does clock skew and setup time calculations now, but does not yet use wire load models.
    Also: Update at Thu Oct 31 20:41:33 EDT 2013 by tim
    Also: Merge branch 'master' into work
  60. November 2, 2013 at 3:00am
    A few more minor optimizations. Inverted "fast mode" so that default mode is "fast" and "--exhaustive" forces an exhaustive search. This was precipitated by the realization that the OSU035 liberty file has nonsensical data in places, such as negative propagation delays, and that for normal, sensible data sets, the fast search's greedy algorithm will always produce the correct result.
    Also: Update at Fri Nov 1 20:08:35 EDT 2013 by tim
    Also: Merge branch 'master' into work
    Also: Removed temporary copies of the vesta source.
  61. November 5, 2013 at 3:00am
    Added the remainder of the standard analysis types to vesta, including minimum path delay register-to-register and register-to-output, and maximum and minimum path delays for input-to-register and input-to-output.
    Also: Update at Mon Nov 4 13:34:58 EST 2013 by tim
    Also: Merge branch 'master' into work
  62. November 27, 2013 at 3:00am
    Important update to the clock tree insertion tool, which now iterates to produce hierarchical trees to whatever depth is needed to maintain maximum fanout counts.
    Also: Update at Tue Nov 26 19:27:07 EST 2013 by tim
    Also: Merge branch 'master' into work
  63. November 28, 2013 at 3:00am
    A number of changes to the flow: Mainly, incorporated the "decongest" script into a second round of place and route, that will run if and only if the router failed to route everything the first time. However, this involved other changes, such as moving the number of layers (if not default) declaration into the project_vars.sh file, reworking the way qrouter is called to parse the LEF file for routing information, so that qrouter is called outside of place2def.tcl, using a simple bootstrap configuration file. place2def only generates the "fence" of obstruction layers around the pins, then dumps this information into a file called ".obs" that is used by the placement script to construct the routing configuration file for qrouter. This rearrangement also corrected a problem where several via configuration statements were being executed after the routing, which means they were not being applied to the routing at all. The new flow with the additional decongestion placement and final routing has been run on several test cases. It shows excellent results with the osu035 standard cell set, although it is likely that the decongestion parameters will need to be changed for other technologies.
    Also: Update at Wed Nov 27 16:21:48 EST 2013 by tim
    Also: Merge branch 'master' into work
    Also: Modified router script to track qrouter's new output messages about "Nets remaining" instead of "TotalRoutes". Yada yada yada. See xkcd 1296.
    Also: HAAAAAAAAAAAANDS (xkcd 1296)
  64. November 29, 2013 at 3:00am
    Reworked the decongestion script both to match the normalized value now produced by qrouter, and to scale up the amount of fill based on the percentage of route failures on the last qrouter run. Also changed the "fanout" feedback to the log file from the inscrutable "nchanged=" to the more obvious "gates resized:".
    Also: Update at Thu Nov 28 12:02:49 EST 2013 by tim
    Also: Merge branch 'master' into work
  65. December 2, 2013 at 3:00am
    Twiddled with the decongestent parameters again. It is clear that continued twiddling will not greatly improve the flow. It is necessary to do a better sorting and masking in qrouter to improve the routing solution, because there are cases of large designs failing to route in spite of having fill added up the wazoo.
    Also: Update at Sun Dec 1 17:17:26 EST 2013 by tim
    Also: Merge branch 'master' into work
  66. December 21, 2013 at 3:00am
    Changes to deal with problems arising from use of lower case in either the macro cell names or the tech directory name.
    Also: Update at Fri Dec 20 13:05:12 EST 2013 by tim
    Also: Merge branch 'master' into work
  67. January 17, 2014 at 3:00am
    Corrected an error where yosys' use of a backslash before module names would get interpreted by the script as unix escape codes. Synthesis script changed to replace the backslash with a forward slash to avoid the error.
    Also: Update at Thu Jan 16 09:14:35 EST 2014 by tim
    Also: Merge branch 'master' into work
  68. January 18, 2014 at 3:00am
    Modified blif2Verilog so that it changes characters ":" and "." to underscores ("_") in all signal names, because these characters are not legal verilog. Because the original verilog source cannot have such signal names, it is not anticipated that this will cause any problems with matching signal names elsewhere in the flow.
    Also: Update at Fri Jan 17 17:05:31 EST 2014 by tim
    Also: Merge branch 'master' into work
  69. January 23, 2014 at 3:00am
    Modified the yosys synthesis script to make use of the new commands for mapping tiehi and tielo standard cells.
    Also: Update at Wed Jan 22 09:56:20 EST 2014 by tim
    Also: Merge branch 'master' into work
  70. January 24, 2014 at 3:00am
    Added the "tiehipin_out" and "tielopin_out" variables to the osu035.sh and osu050.sh scripts, although there are no tie cells in those standard cell sets, mostly to let people know that the method is available, and how to use it.
    Also: Update at Thu Jan 23 21:23:12 EST 2014 by tim
    Also: Merge branch 'master' into work
  71. January 26, 2014 at 3:00am
    Made changes to the flow scripts so that (1) the flow properly detects when yosys has failed to generate a new output blif file, and will stop; and (2) each script of the flow will fail to run if the previous script has stopped due to a fatal error. The combination of these changes prevents qflow from continuing to run and producing output based on results of some previous run.
    Also: Update at Sat Jan 25 12:26:24 EST 2014 by tim
    Also: Merge branch 'master' into work
  72. February 7, 2014 at 3:00am
    Made a change to the placement script to check if "qrouter -i" generated an output ".info" file and halt if not. This prevents the placement from otherwise proceeding on to the place2def.tcl script and failing with an unhelpful and obscure error message.
    Also: Update at Thu Feb 6 12:06:04 EST 2014 by tim
    Also: Merge branch 'master' into work
  73. February 8, 2014 at 3:00am
    Corrected an error pertaining to the order in which qrouter is told to read the technology and macro LEF files. This was corrected in the section of code that writes the configuration file for the Tcl-based version of qrouter but was not fixed in the section of code that writes a slightly different syntax of configuration file for the non-Tcl-based version of qrouter.
    Also: Update at Fri Feb 7 12:38:22 EST 2014 by tim
    Also: Merge branch 'master' into work
  74. February 9, 2014 at 3:00am
    Corrected an error in vesta that would invert the tables, swapping times with capacitances, with obviously bad results.
    Also: Update at Sat Feb 8 11:29:24 EST 2014 by tim
    Also: Merge branch 'master' into work
  75. February 16, 2014 at 3:00am
    A very quick fix to ybuffer.tcl to correct an error that could produce a bad output netlist when any output name is a substring of another output name. However, this should be replaced shortly with a better implementation within yosys.
    Also: Update at Sat Feb 15 15:58:44 EST 2014 by tim
    Also: Merge branch 'master' into work
    Also: Updated synthesize_yosys to make use of the "-bits" option to the "iopadmap" command in yosys v.0.2.0. This replaces the use of script "ybuffer.tcl" to insert output buffers, and is more general in that it can also be used to add input buffers or handle bidirectional ports, although anything beyond adding output buffers requires a custom synthesis script.
  76. February 17, 2014 at 3:00am
    Corrected Vesta for lookup tables that are 1-dimensional.
    Also: Update at Sun Feb 16 17:15:48 EST 2014 by tim
    Also: Merge branch 'master' into work
  77. April 9, 2014 at 3:00am
    Added routine "getfillcell.tcl" that searches a LEF file for fill cells according to the pattern given in the tech setup shell script, and a .par file with a feedThruWidth definition, and returns the name of the fill cell whose width matches the one used in the .par file.
    Also: Update at Tue Apr 8 17:42:20 EDT 2014 by tim
    Also: Merge branch 'master' into work
  78. May 27, 2014 at 3:00am
    Update at Mon May 26 09:55:12 EDT 2014 by tim
  79. May 28, 2014 at 3:00am
    Update at Tue May 27 19:10:21 EDT 2014 by tim
  80. May 30, 2014 at 3:00am
    Update at Thu May 29 10:52:52 EDT 2014 by tim
  81. May 31, 2014 at 3:00am
    Update at Fri May 30 14:41:25 EDT 2014 by tim
  82. June 1, 2014 at 3:00am
    Update at Sat May 31 14:50:58 EDT 2014 by tim
  83. July 10, 2014 at 3:00am
    Correction to the clocktree script to handle cells such as tiehi/ tielo that have no inputs, instead of generating an error and exiting.
    Also: Update at Wed Jul 9 12:00:47 EDT 2014 by tim
    Also: Merge branch 'master' into work
  84. July 13, 2014 at 3:00am
    Additional diagnostic statements printed in the STA tool.
    Also: Update at Sat Jul 12 14:18:44 EDT 2014 by tim
    Also: Merge branch 'master' into work
    Also: Fixed an error that causes vesta to crash if it has bad input and cannot find a valid netlist.
    Also: Corrected an error in blifFanout that causes a crash if the gate strength changes from a 1-character suffix (e.g., "1") to a 2-character suffix (e.g., "10").
  85. July 18, 2014 at 3:00am
    Added support for structural verilog in-line, pending update of yosys to revision 0.3.1.
    Also: Update at Thu Jul 17 08:34:09 EDT 2014 by tim
    Also: Merge branch 'master' into work

Revision information prior to qflow system:

  1. Date: June 19, 2011
    Initial offering of the full digital flow with the new open-source detail router qrouter.

  2. Date: June 21, 2011
    Modified the bdnet2cel.tcl script to do much more thorough parsing of the LEF file, including ignoring various sections that are normally found in LEF files (but not needed by the converter script), and parsing layer information for track pitches. The pins must be declared with dimensions equal to the route pitches, because TimberWolf will place pins next to each other, and if they are placed closer together than the route pitch, they will overlap and not be routable.

  3. Date: December 6, 2012
    Made substantial updates to the place2def2.tcl script. This corrects for track offset from the origin and also corrects an error that gave all the pin positions an offset that could potentially drop the pins outside of the routing track area, making them unroutable.
  4. Date: December 7, 2012
    Added clocktree.tcl to the list of files to download. This script tool breaks up large fanout nets (like the clock) with buffer trees. It is not particularly useful without the load balancing tool that I have not yet converted to a generic process.

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Last updated: September 23, 2017 at 3:00am