`timescale 1 ps/ 1fs 

/* 
   This maps N (binary into the shift_cmos divider input.
   This should be synthesizable
*/

module map9v3( clock, reset, start, N, dp, done );


input         clock;
input	      start;         // run at rising edge of start
input	      reset;         // high is reset case ( run after reset)
input   [8:0] N;             // the number to divide by
output  [8:0] dp;	     // inputs to shift_cmos
output	      done;

reg    [8:0] dp;	   

reg	[7:0] sr;
reg	[7:0] counter;
reg	      oldstart;
reg	      run;
reg	      tmp;
reg	      almostdone;
reg	      done;
reg	      oldreset;



always @(posedge clock) begin


        done = almostdone;
        almostdone = ~run;
	if( run == 1 ) begin
	    tmp = ~(sr[7] ^ sr[5] ^ sr[4] ^ sr[3]);
	    sr[7] = sr[6];
	    sr[6] = sr[5];
	    sr[5] = sr[4];
	    sr[4] = sr[3];
	    sr[3] = sr[2];
	    sr[2] = sr[1];
	    sr[1] = sr[0];
	    sr[0] = tmp;
	    counter = counter -1;
	    if( counter == 0 ) 		run = 0;
	end else if( ((start == 1 && oldstart == 0)  ||
	              (reset == 0 && oldreset == 1)     )
		     && ~reset ) begin
	    counter = 255- N[8:1] + 3;
	    sr = 8'b0;
	    run = 1;
	end 
	oldstart = start;
	oldreset = reset;
	if( done == 0 && almostdone == 1) begin
	    dp[0] = N[0];
	    dp[8:1] = sr[7:0];
	end
	if( reset == 1 ) begin
	    sr = 8'b0;
	    run = 0;
	end
	
end



endmodule