# intrinsic delay at Load=0.1p

GATE AND2X1 3.2  Y = ( A * B );
  PIN A NONINV 0.05 0.9494 0.2200 3.1600 0.1200 2.00
  PIN B NONINV 0.05 0.9494 0.2200 3.1600 0.1200 2.00

GATE AOI21X1 3.2 Y = ! ( (A * B) + C );
  PIN A INV 0.07 1 0.50 2.92 0.40 2.05
  PIN B INV 0.07 1 0.50 2.92 0.40 2.05
  PIN C INV 0.07 1 0.50 2.92 0.40 2.05

GATE AOI22X1 4.0 Y = ! ( (A * B) + (C * D) );
  PIN A INV 0.07 1 0.50 2.92 0.40 2.05
  PIN B INV 0.07 1 0.50 2.92 0.40 2.05
  PIN C INV 0.07 1 0.50 2.92 0.40 2.05
  PIN D INV 0.07 1 0.50 2.92 0.40 2.05

GATE OAI21X1 3.2 Y = ! ( (A + B) * C );
  PIN A INV 0.07 1 0.50 2.92 0.40 2.05
  PIN B INV 0.07 1 0.50 2.92 0.40 2.05
  PIN C INV 0.07 1 0.50 2.92 0.40 2.05

GATE OAI22X1 4.0 Y = ! ((A + B) * (C + D));
  PIN A INV 0.07 1 0.50 2.92 0.40 2.05
  PIN B INV 0.07 1 0.50 2.92 0.40 2.05
  PIN C INV 0.07 1 0.50 2.92 0.40 2.05
  PIN D INV 0.07 1 0.50 2.92 0.40 2.05

GATE BUFX2   2.4 Y = A;
 PIN A NONINV 0.02 1.0 0.14 3.1800 0.09 2.9000

GATE INVX1   1.6 Y = ! A;
 PIN A INV 0.04 1.0 0.07 3.1800 0.09 2.9000

GATE OR2X1  3.2 Y = (A + B);
 PIN A NONINV 0.09 1.0 0.85 2.97 0.74 2.91
 PIN B NONINV 0.09 1.0 0.85 2.97 0.74 2.91

GATE XOR2X1  5.6 Y = ((!A * B) + (A * !B));
 PIN A UNKNOWN 0.09 1.0 0.85 2.97 0.74 2.91
 PIN B UNKNOWN 0.09 1.0 0.85 2.97 0.74 2.91

GATE XNOR2X1  5.6 Y = !((!A * B) + (A * !B));
 PIN A UNKNOWN 0.09 1.0 0.85 2.97 0.74 2.91
 PIN B UNKNOWN 0.09 1.0 0.85 2.97 0.74 2.91

GATE NAND2X1 2.4 Y = ! (A * B);
  PIN A INV 0.05 0.9494 0.2200 3.1600 0.1200 2.00
  PIN B INV 0.05 0.9494 0.2200 3.1600 0.1200 2.00

GATE NAND3X1 3.2 Y = ! (A * B * C);
 PIN A INV 0.05 0.9494 0.2200 3.1600 0.1200 2.00
 PIN B INV 0.05 0.9494 0.2200 3.1600 0.1200 2.00
 PIN C INV 0.05 0.9494 0.2200 3.1600 0.1200 2.00

GATE NOR2X1  2.4  Y = ! (A + B);
 PIN A INV 0.06 1.0 0.2100 2.9200 0.3200 2.9500
 PIN B INV 0.06 1.0 0.2100 2.9200 0.3200 2.9500

GATE NOR3X1  6.4  Y = ! (A + B + C);
 PIN A INV 0.06 1.0 0.2100 2.9200 0.3200 2.9500
 PIN B INV 0.06 1.0 0.2100 2.9200 0.3200 2.9500
 PIN C INV 0.06 1.0 0.2100 2.9200 0.3200 2.9500

GATE MUX2X1 4.8 Y = ! ((S * A) + (!S * B));
 PIN A UNKNOWN 0.03 0.9524 0.64 3.150 0.74 2.930 
 PIN B UNKNOWN 0.03 0.9524 0.64 3.150 0.74 2.930 
 PIN S UNKNOWN 0.05 0.9524 0.48 3.150 0.54 2.930 

LATCH DFFPOSX1 9.6 Q = D;
PIN D NONINV 0.02 0.9494 1.4600 3.1600 1.7500 2.9200
SEQ Q ANY RISING_EDGE
CONTROL CLK 0.02 0.9494 1.4600 3.1600 1.7500 2.9200
CONSTRAINT D 0.70 0.0

LATCH DFFNEGX1 9.6 Q = D;
PIN D NONINV 0.02 0.9494 1.4600 3.1600 1.7500 2.9200
SEQ Q ANY FALLING_EDGE
CONTROL CLK 0.02 0.9494 1.4600 3.1600 1.7500 2.9200
CONSTRAINT D 0.70 0.0

GATE LOGIC0	0	O=CONST0;
GATE LOGIC1	0	O=CONST1;