#!/bin/tcsh -f
#
# /pub/tech/Jazz/verilog/synth_script.sh:
#-------------------------------------------------------------------------
#
# This script synthesizes verilog files.
#-------------------------------------------------------------------------
# November 2006
# Tim Edwards
# Open Circuit Design
#-------------------------------------------------------------------------

if ($#argv < 2) then
   echo Usage:  synth_script.sh <technology> [options] <vname>
   exit 1
endif

set techname=${argv[1]:al}
set argline=`getopt "c:b:f:nx" $argv[2-]`
set options=`echo $argline | awk 'BEGIN {FS = "-- "} END {print $1}'`
set cmdargs=`echo $argline | awk 'BEGIN {FS = "-- "} END {print $2}'`
set argc=`echo $cmdargs | wc -w`

rm -f synth.log >& /dev/null
touch synth.log

#---------------------------------------------------------------------
# check host and number of arguments. . .
#---------------------------------------------------------------------

if ("${techname}" == "osu018") then
   set flopcell=DFFPOSX1
   set bufcell=BUFX2
   set leffile=osu018_stdcells.lef
else
   echo "Don't know about technology '${techname}'.  Use OSU018"
   exit 1
endif

if ($argc == 2) then
   set argv1=`echo $cmdargs | cut -d' ' -f1`
   set argv2=`echo $cmdargs | cut -d' ' -f2`
else if ($argc == 1) then
   if (!( -f /usr/local/bin/vis )) then
      echo "No executable /usr/local/bin/vis"
      exit 1
   endif
   set argv1=`echo $cmdargs`
else
   echo Usage:  synth_script.sh <technology> [options] <vname> [<lname>]
   echo   where
   echo	      <technology> is "O18" (choices to be expanded. . .)
   echo	      <vname> is the root name of the verilog file (including path), and
   echo	      [<lname>] is the root name of the layout (.mag) file (no path).
   echo	      [options] are passed verbatim to the AddIOToBDNet program
   exit 1
endif

set rootname=${argv1:t:r}
set srcdir=${argv1:h}

#---------------------------------------------------------------------------
# Find the file.  We assume a directory structure in which the source file
# is either in the current working directory or some searchable subdirectory
# of it.  We create subdirectory "synthesis" where we will put all output
# files from the synthesis part of the flow.
#---------------------------------------------------------------------------

set curdir=`pwd`
set fullpath=`find . -name ${rootname}.v -print`
set found=`echo $fullpath | wc -w`
if ($found > 1) then
   set srcdir=${fullpath[1]:h}
   set topdir=${srcdir:h}
else if ($found == 1) then
   set srcdir=${fullpath:h}
   set topdir=${srcdir:h}
else 
   if ($srcdir == ${argv1:t}) then
      set srcdir="."
      set topdir="."
   else
      set topdir=${srcdir:h}
   endif
endif

vis >>& synth.log << EOF
read_verilog ${srcdir}/${rootname}.v
write_blif ${srcdir}/${rootname}.blif
quit
EOF

#---------------------------------------------------------------------
# Check for verilog compile-time errors
#---------------------------------------------------------------------

set errline=`cat synth.log | grep "No file has been read in" | wc -l`
if ( $errline == 1 ) then
   echo ""
   echo "Verilog compile errors occurred:"
   echo "See file synth.log for details."
   echo "----------------------------------"
   cat synth.log | grep "^line"
   echo ""
   exit 1
endif

sis >> synth.log << EOF
read_blif ${srcdir}/${rootname}.blif
rlib ${techname:al}.genlib

sweep; eliminate -1
simplify -m nocomp
eliminate -1

sweep; eliminate 5
simplify -m nocomp
resub -a

fx
resub -a; sweep

eliminate -1; sweep
full_simplify -m nocomp

map -n 0 -s
write_bdnet ${srcdir}/${rootname}.bdnet
quit
EOF

echo ""
echo "Please check ${srcdir}/${rootname}.bdnet with a text editor."
echo "Right column numbers must be unique."
echo ""

set synthdir=${topdir}/synthesis
mkdir -p ${synthdir}

#---------------------------------------------------------------------
# Check whether any clocks are used before automatically inserting one...
#---------------------------------------------------------------------

set opt1=`echo $options | cut -d' ' -f 1`
set clkpins=`cat ${srcdir}/${rootname}.bdnet | grep -c UNCONNECTED`

if ( "$opt1" == "-x" || "$opt1" == "-c" || "$clkpins" > 0 ) then
    sed s/'UNCONNECTED;'/'"clock";'/ < ${srcdir}/${rootname}.bdnet | \
	sed -e '/^INPUT/a\\
	"clock" : "clock"' > ${synthdir}/${rootname}.bdnet
else
    cp ${srcdir}/${rootname}.bdnet ${synthdir}/${rootname}.bdnet
endif

#---------------------------------------------------------------------
# Add buffers for the O18 library
#---------------------------------------------------------------------

if ("$opt1" == "-x") then
   echo "Adding output buffers and clocked input buffers."
else
   echo "Adding output buffers only.  Use -x if you want clocked input buffers."
endif

AddIO2BDnet -t /pub/tech/Jazz/verilog/jazz${techname:al}.genlib \
	-b ${bufcell} -f ${flopcell} $options \
	${synthdir}/${rootname}.bdnet > ${synthdir}/${rootname}_tmp.bdnet

echo "Cleaning up bdnet file syntax (removing characters <, >, trailing 0's)."
CleanUpBdnet -b ${synthdir}/${rootname}_tmp.bdnet > \
	${synthdir}/${rootname}_buf.bdnet

rm -f ${synthdir}/${rootname}_tmp.bdnet >& /dev/null

echo ""
echo "Generating RTL verilog and SPICE netlist file in directory ${synthdir}"
echo "Files:"
echo "   Verilog: ${synthdir}/${rootname}.rtl.v"
echo "   Verilog: ${synthdir}/${rootname}.rtlnopwr.v"
echo "   SPICE:   ${synthdir}/${rootname}.net"
echo "   SPICE:   ${synthdir}/${rootname}.spi"
echo ""

echo "Running Bdnet2Verilog."
Bdnet2Verilog ${synthdir}/${rootname}_buf.bdnet \
	> ${synthdir}/${rootname}.rtl.v

cat ${synthdir}/${rootname}.rtl.v | \
	sed s/".VSS(VSS), .VDD(VDD),"/" "/ \
	> ${synthdir}/${rootname}.rtlnopwr.v

echo "Running Bdnet2BSpice."
Bdnet2BSpice ${synthdir}/${rootname}_buf.bdnet \
	> ${synthdir}/${rootname}.net

cat ${synthdir}/${rootname}.net | sed s/"vdd vss "/"  "/ \
	> ${synthdir}/${rootname}.spi

cd ${curdir}

#-------------------------------------------------------------------------
# Clean up after myself!
#-------------------------------------------------------------------------

rm -f ${rootname}.enc >& /dev/null
rm -f /tmp/vis.* >& /dev/null

#-------------------------------------------------------------------------
# Create the .cel file for TimberWolf
#-------------------------------------------------------------------------

set layoutdir=${topdir}/layout
mkdir -p ${layoutdir}

echo "Running bdnet2cel.tcl"
bdnet2cel.tcl ${synthdir}/${rootname}_buf.bdnet ${leffile} \
	${layoutdir}/${rootname}_buf.cel
cp ${techname:al}.par ${layoutdir}/${rootname}_buf.par

echo "Edit ${layoutdir}/${rootname}_buf.par, then run TimberWolf"