Thank you for visiting the Open Circuit Design website. This website is the repository for the suite of open-source EDA (Electronic Design Automation) tools including Magic, IRSIM, Netgen, PCB, and XCircuit. These tools are all provided for free under the GNU Public License (GPL) or similar open-source license.
Open Circuit Design is committed to keeping open-source EDA tools useful and competitive with commercial tools.
Click on the buttons in the menu on the left to get to the home page of each of the major electronic design automation (EDA) tools hosted by Open Circuit Design:
- Magic, the VLSI layout editor, extraction, and DRC tool.
- XCircuit, the circuit drawing and schematic capture tool.
- IRSIM, the switch-level digital circuit simulator.
- Netgen, the circuit netlist comparison (LVS) and netlist conversion tool.
- Qrouter, the over-the-cell (sea-of-gates) detail router.
- Qflow, a complete digital synthesis design flow using open-source software and open-source standard cell libraries.
- PCB, the printed circuit board layout editor.
efabless.com hosts Open Circuit Design software! efabless is the company where I work, and is bringing community collaboration to the process of circuit design. Getting an account on efabless is free, so get yourself access to the platform today!
A core component of the efabless platform is CACE, the Circuit Automatic Characterization Engine. Spec sheets for circuits are built in a rigorous framework that tells the characterization engine how to completely test the circuit for performance limits under all conditions. CACE can be run locally on the design environment in conjunction with schematic entry, layout, and simulation, and it can be run remotely to submit a design to the efabless marketplace. It turns the spec sheet into a datasheet and gives the circuit a "pass" or "fail" grade for each measured parameter and for the circuit overall.
Part of the efabless platform is to host challenges and award prizes for winning circuit designs, as well as provide a marketplace for creating, buying, and selling integrated circuit intellectual property.
efabless launched its first challenge on November 29, 2016. This challenge is now closed for new entrants, but more challenges will be forthcoming. Go to the company website for more information.
When the first challenge went into its second stage, in Februrary 2017, the efabless platform was updated with Magic for layout and extraction, and Netgen for LVS. Magic got an overhaul of the PDK API, while netgen got an overhaul to handle passive device networks in serial and parallel combinations, and got a new GUI interface on the efabless platform.
Qflow is featured as part of "cloudv", the digital synthesis and verification system on the efabless platform. "Cloudv" is a cloud-based UI wrapper around yosys synthesis, and integrates with the rest of the efabless platform. Qflow and qrouter are used on the platform for the backend part of the synthesis flow (place and route, physical verification).
In the spring of 2018, I used the efabless platform to create a RISC-V microprocessor on the X-Fab XH018 process. The entire design (based on the PicoRV32 core by Clifford Wolf) took only a few months. It taped out in August and came back in December. I tested in January and February 2019, and proved that qflow can provide first time success on silicon. The processor has over 20,000 logic cells and runs at 100MHz core clock rate. The chip has 1k x 32 bits on-board RAM, interfaces to an external SPI flash memory, and features integrated analog circuit functions including two ADCs, a DAC, bandgap, temperature alarm, comparator, and RC oscillator.
See my interview on EEWeb for a pretty concise summary of what Open Circuit Design and EDA tool open source development mean to me.
The OpenCircuitDesign domain is owned by me (Tim Edwards) and registered through DNSexit.com. Initially, I ran it off of a computer in my basement in Maryland and tracked the Comcast dynamic IP address using the DynDNS service. After that, for some years the OpenCircuitDesign computer sat in the network closet at MultiGiG in Scotts Valley, California, where it had a fixed IP address. Since 2012, it is back in my basement in Maryland. The OpenCircuitDesign host computer is a Fedora Core system. The underlying network service is now Comcast Xfinity (because Verizon FiOS won't cross the road).
OpenCircuitDesign.com runs a Wiki service using UseMod software, mailing lists using MailMan, a bug tracking database using Bugzilla, and spam filtering using SpamAssassin. It runs an IMAP mail server for inbound mail. Outbound mail is handled via Google. HTDig is installed as the search engine for the site, which is also integrated into MailMan for searching the mailing list archive.
As of May 2011, all of the primary software projects are placed under git, the software versioning system created for Linux development. This is a slight update from the previous system, dating from April 2006, in which all projects were placed under CVS (concurrent versions system). Since I normally prefer tarballing distributions regularly, I have instituted a complicated system of scripts on OpenCircuitDesign. I have a copy of all the source distributions on OpenCircuitDesign in git repositories. At the end of the day (during the night), cron launches a script that checks each project, and does the following:
As part of all this activity, the script is careful to keep separate the "stable" and "development" distributions where I have both (e.g., Magic and XCircuit).
- Determines if any commits have been made during the day. If not, no further action is taken. Otherwise:
- Updates the revision number of the project
- Creates a new tarball
- Updates the download web page to point to the new tarball
- Compiles all of the commit messages since the last tarball was made
- Appends the messages to the history ("changes") web page.
A separate cron script runs roughly once a week, checking the "last modified" date on each file in the website and updating the "Last Updated" message at the bottom of each web page if it is different, so I don't have to.