R. Timothy Edwards

email:

Current Prospects:

I an active contributor to the Google/SkyWater and Google/Global Foundries Open PDK projects, helping to create, correct, and maintain the Open PDK repositories. I have authored and maintain the software package open_pdks for building PDKs that are compatible with many open-source tool flows.

The IHP GmbH foundry in Germany open sourced the PDK for their SG13G2 process, and used my open_pdks format as the structure for their open PDK. I have also contributed to the IHP open PDK.

I actively maintain a package of free, open-source EDA tools for analog and digital VLSI design. The analog design flow includes magic for VLSI layout, ngspice for simulation, xcircuit for schematic capture, netgen for LVS, and pcb for circuit board layout. The digital design flow includes qflow to manage the overall synthesis design flow, yosys to synthesize logic from verilog source, timberwolf to do standard cell placement, vesta for static timing analysis, and qrouter for detail routing. I have authored the tools xcircuit, qflow, vesta, and qrouter, and have greatly improved the tools magic, IRSIM, and netgen through continued development.

My most recent software projects are CACE (Circuit Automatic Characterization Engine), for full automated characterization of analog and mixed-signal circuits, and capiche, a tool for modeling parasitic capacitance in a foundry process using the "fastercap" field equation solver.

Since Efabless Corporation shut down at the end of Februrary, 2025, I am working as a contractor and consultant and spending time on open source silicon advocacy.

Research Interests:

Open-source EDA (Electronic Design Automation) tools (algorithm development, programming, maintenance, and distribution).

Also: Architectures and algorithms for ``Evolvable hardware'', field-programmable analog hardware, novel MEMS technology for reconfigurable hardware interconnect, and ``neuromorphic'' (biologically-motivated) systems.

Education:

• 9/93 to 3/99 Johns Hopkins University, Baltimore, MD.
  Ph.D. in Electrical Engineering, researching Analog VLSI with Drs. Gert Cauwenberghs (thesis advisor) and Andreas Andreou.
  Thesis: Time-Frequency Acoustic Processing and Recognition: Analysis and Analog VLSI Implmentations.
• 9/90 to 6/92 Stanford University, Stanford, CA.
  M.S. in Electrical Engineering (MSEE)
  Emphasis on (digital) VLSI custom and semicustom design, signal processing, neural networks, and Analog VLSI systems.
• 8/86 to 5/90 Duke University, Durham, NC.
  B.S. in Electrical Engineering (BSEE)
  Satisfied requirements for B.S. in Physics
  GPA = 3.92/4.00, class rank (School of Engineering) = 7/270
  Emphasis during last two years on computer architecture, pattern recognition and classification, and neural networks.

Teaching Experience:

• 7/93 to 6/94, 1/95 to 6/95 Johns Hopkins University, Baltimore, MD.
  Taught lecture and lab courses in undergraduate microelectronics in the JHU part-time program. Student evaluations are available upon request.
• 12/91 to 3/92 Stanford University, Stanford, CA. ISL, Electrical Engineering Dept.
  Worked as a teaching assistant for Dr. Abbas El-Gamal, EE-218, ``Semi-Custom VLSI''; included teaching and managing the laboratory part of the course.
• Summer 2020 through 2024. Mentor for high school interns, especially for the Poolesville High School (Maryland) SMCS (Science, Math, and Computer Science) magnet program.
• Summer 2022 and 2023. Google Summer of Code (GSoc) mentor in the FOSSi (Free and Open-Source Silicon) group.

Research and Work Experience:

• 3/35 to present Open Circuit Design, LLC, Poolesville, MD.
  Contract and consulting work. Open source silicon advocacy.
• 9/21 to 9/23 NIST, Gaithersburg, MD.
  Associate. Consulting with the Nanofabrication lab on test measurements of the SkyWater sky130 process.
• 7/16 to 2/25 Efabless, Inc., San Jose, CA.
  Senior vice president of analog and platform. Responsible for developing the tools for community-contributed circuit design. Includes working with foundries to enable their processes on the Efabless platform, working with designers to get IP into the Efabless marketplace catalog, working with customers to create design challenges for the community, and continually enhancing tools and methods for analog, digital, and full-chip assembly flows.
  
• 2/12 to 6/16 Analog Devices, Inc., San Jose, CA.
  Design engineer in clock and signal generation product development, an extension of the product development done at MultiGiG, which was bought by Analog Devices in 2012.
  
• 6/05 to 2/12 MultiGiG, Inc., Scotts Valley, CA.
  Principal design engineer for research and product development of the Rotary Traveling Wave Oscillator (RTWO) technology.
  
• 11/98 to 6/05 Johns Hopkins University Applied Physics Laboratory, Laurel, MD.
  Investigator on Advanced Technology Development (ATD) program targeting the development of Field-Programmable Analog Array (FPAA) devices for space applications.
  Principal Investigator with Chang-Jiang Kim at UCLA on a NASA grant project to develop a fabrication process for mercury microswitch MEMS technology.
  Principal Investigator for a project investigating the use of template correlation methods for emulating dolphin sonar for buried target classification.
  
• 6/95 to 3/99 Johns Hopkins University, Baltimore, MD.
  Research assistant for Dr. Gert Cauwenbergs. Joint projects with the Army Research Laboratory and with Dr. Fernando Pineda at the Johns Hopkins Applied Physics Laboratory (APL).
• 6/94 to 12/94 Johns Hopkins University, Baltimore, MD.
  Research assistant for Dr. Andreas Andreou.
• 2/91 to 6/93 Stanford University, Stanford, CA.
  Helped visiting professor Michael Godfrey create a laboratory for research in analog VLSI; worked on research projects including an electronic cochlea with Neal Bhadkamkar and MOS transistor modeling with Dr. Michael Godfrey.
• 7/92 to 12/92 Zilog Corporation, Campbell, CA.
  Designed an Analog VLSI continuous wavelet transform chip for use in a low-power speech compression system as part of Zilog's telephone answering machine project. Several versions of this chip were fabricated by Zilog; development of the idea was completed at Johns Hopkins University.
• 3/92 to 6/92 Stanford University, Stanford, CA. ISL, Electrical Engineering Dept.
  Worked as a research assistant maintaining and updating the EE-218 (semicustom VLSI) laboratory.
• 9/91 to 12/91 Stanford University, Stanford, CA. STAR Laboratory, EE Dept.
  Worked as a system administrator for a group of workstations, including installation and maintenance of CAD software.
• 6/91 to 8/91 Star Semiconductor, Inc., Warren, NJ.
  Designed and implemented a discrete wavelet transform decomposition and reconstruction system as an application note for the Star Semiconductor SPROClab DSP development system.
• 5/90 to 8/90 Continuous Electron Beam Accelerator Facility (CEBAF), Newport News, VA. Physics Division
  Wrote several thousand lines of FORTRAN code to create a complete data acquisition and display program for a full-scale prototype particle detection chamber. The final product met all standards for the VAX/VMS operating system.
• 5/89 to 8/89 CEBAF Physics Division
  Wrote FORTRAN software for a data acquisition system, designed and built a laser-based calibration system for particle detection equipment.

Journal Publications:

• Q. Zhang, W. Duan, T. Edwards, T. Ansell, D. Blaauw, D. Sylvester, M. Saligane, ``An Open-Source and Autonomous Temperature Sensor Generator Verified With 64 Instances in SkyWater 130 nm for Comprehensive Design Space Exploration'' IEEE Solid-State Circuits Letters, vol. 5, July 2022, pp. 174-177.
• R. Timothy Edwards, Mohamed Shalan, and Mohamed Kassem, ``Real Silicon Using Open-Source EDA'' IEEE Design and Test, vol. 38, no. 2, March/April 2021, pp. 38-44.
• T.-R. Lin, T. Edwards, M. Pedram, ``qGDR: A Via-Minimization-Oriented Routing Tool for Large-Scale Superconductive Single-Flux-Quantum Circuits,'' IEEE Trans. on Applied Superconductivity, vol. 29, no. 7, Oct. 2019.
• R. T. Edwards, M. Cohen, G. Cauwenberghs, M. Vorontsov, and G. Carhart, ``Analog VLSI Parallel Stochastic Optimization for Adaptive Optics,'' Learning on Silicon, Gert Cauwenberghs, ed., Kluwer publishers (1999).
• R. T. Edwards and G. Cauwenberghs, ``Mixed-Mode Correlator for Micropower Acoustic Transient Classification,'' J. Solid-State Circuits, vol. 34, no. 10, pp. 1367-1372.
• R. T. Edwards and G. Cauwenberghs, ``Synthesis of Log-Domain Filters from First-Order Building Blocks,'' (to appear in) Int. J. Analog Integrated Circuits and Signal Processing, special issue on ``Dynamic Translinear Circuits''.
• R. T. Edwards and G. Cauwenberghs, ``Oversampling Architecture for Analog Harmonic Modulation,'' IEEE Trans. on Circuits and Systems, vol. 43, no. 8, pp. 696-698.
• F. Pineda, G. Cauwenberghs, R. T. Edwards, K. Ryals, and D. Steigerwald, ``Bang, Click, Thud, or Whack?'' Johns Hopkins APL Technical Digest, vol. 18, no. 2, pp. 244-253.

Selected Conference Publications:

• T. Edwards, ``Caravel Panamax: The Next Generation,'' FSiC, Paris, France, 2024.
• T. Edwards, ``CACE Study: Open source analog & mixed-signal design flow,'' FOSSi Latch-Up, April 20, 2024, Boston, Massachusetts.
• T. Edwards, ``Principles of Paranoid Design,'' OSDA, April 17, 2023, Antwerp, Belgium.
• T. Edwards, ``Whom do you trust?: Validating process parameters for open-source tools,'' FSiC, Paris, France, 2022.
• T. Edwards and M. Shalan, ``The Efabless Caravel project---Chip design for the software-oriented,'' COSCUP, Aug. 1, 2021.
• T. Edwards, ``Google/SkyWater and the Promise of the Open PDK,'' >Workshop on Open Source EDA Technology (WOSET), 2020.
• T. Edwards, ``Bootstrapping a real working design flow,'' Workshop on Open Source Hardware (WOSH), June 11-14, 2019, Zurich, Switzerland.
• T. Edwards, ``The New Golden Age of Open Silicon,'' (Keynote presentation), Workshop on Open Source EDA Technology (WOSET), 2019.
• R. T. Edwards and C.-J. Kim, ``Breaking the Resistivity Barrier,'' Proceedings of the Third NASA/DoD Workshop on Evolvable Hardware (EH-2001), IEEE Computer Society, pp. 167-171, July, 2001.
• R. T. Edwards, ``Acoustic Transient Classification with a Template Correlation Processor,'' 2nd European Workshop on Neuromorphic Systems, Stirling, Scotland, Sept. 1999.
• R. T. Edwards, K. Strohbehn, S. E. Jaskulek, and R. Katz, ``Analog Module Architecture for Space-Qualified Field-Programmable Mixed-Signal Arrays,'' 2nd annual Military and Aerospace Applications of Programmable Devices and Technologies Conference (MAPLD), JHU-APL, Laurel, MD, October 1999.
• R. T. Edwards and G. Cauwenberghs, ``Log-Domain Circuits for Auditory Signal Processing,'' 42nd Midwest Symposium on Circuits and Systems (MWSCAS), New Mexico State University, August, 1999.
• M. Cohen, R. T. Edwards, G. Cauwenberghs, M. Vorontsov, and G. Carhart, ``AdOpt: Analog VLSI Stochastic Optimization for Adaptive Optics,'' International Joint Conference on Neural Networks, Washington, DC, July 1999.
• R. T. Edwards, G. Cauwenberghs, and F. Pineda, ``Optimizing Correlation Algorithms for Hardware-based Transient Classification,'' Neural Information Processing Systems (NIPS), Denver, 1998.
• R. T. Edwards and G. Cauwenberghs, ``A Second-Order Log-Domain Bandpass Filter for Audio Frequency Applications,'' Int'l Symp. on Circuits and Systems (ISCAS), Monterey, CA, June, 1998.
• R. T. Edwards, G. Cauwenberghs, and F. Pineda, ``Acoustic Transient Classification with Micropower VLSI Neuromorphic Processors,'' 5th Annual Battlefield Acoustics Symposium, United States Army Research Laboratory, Adelphi, MD, September 1997.
• R. T. Edwards, G. Cauwenberghs, and F. Pineda, ``A Mixed-Signal Correlator for Acoustic Transient Classification,'' Proc. ISCAS '97, vol. 1, pp. 621-625, June, 1997.
• F. Pineda, G. Cauwenberghs, and R. T. Edwards, ``Bangs, Clicks, Snaps, Thuds, and Whacks: An Architecture for Acoustic Transient Processing,'' Neural Information Processing Systems (NIPS), Denver, 1996.
• R. T. Edwards and G. Cauwenberghs, ``A VLSI Implementation of the Continuous Wavelet Transform,'' Proc. ISCAS '96, vol. 4, pp. 368-371, May, 1996.
• R. T. Edwards and G. Cauwenberghs, ``Analog VLSI Processor Implementing the Continuous Wavelet Transform,'' Neural Information Processing Systems (NIPS), Denver, 1995.
• T. Edwards and M. Godfrey, ``An Analog Wavelet Transform Chip,'' IEEE Int'l Conf. on Neural Networks, vol. 3, 1993, pp. 1247-1251.

Patents:

• B. Irissou, J. M. Hughes, L. Lanza, M. K. Kassem, M. S. Wishart, R. Srivastava, R. Bell, R. T. Edwards, S. Eid, and G. Shaurette, Systems and methods for obfuscating a circuit design. U.S. Patent no. 11,301,609, U.S. Patent no. 10,423,748.
• B. Irissou, J. M. Hughes, L. Lanza, M. K. Kassem, M. S. Wishart, R. Srivastava, R. Bell, R. T. Edwards, S. Eid, and G. Shaurette, Methods for engineering integrated circuit design and development. U.S. Patent no. 11,182,526, U.S. Patent no. 10,452,802, U.S. Patent no. 10,437,953.
• R. T. Edwards and M. D. Godfrey, Analog wavelet transform circuitry. U.S. Patent no. 5,495,554.
• F. Pineda, G. Cauwenberghs, and R. T. Edwards, Methods and apparatus for acoustic transient processing. U.S. Patent no. 6,389,377.

Honors and Awards:

• Phi Beta Kappa
• Tau Beta Pi
• Graduation Summa Cum Laude and with distinction (Duke University 1990)
• Eta Kappa Nu Electrical Engineering honor society (president, 1989-1990)

Last updated: March 10, 2025 at 11:26am