Open Circuit Design / Chipalooza

Schedule

Five shuttle challenges across three open-source PDKs, spaced roughly three months apart, running 2026–2028.

Challenge #2 (IHP SG13CMOS5L) is currently underway. Proposals are due July 27, 2026, with a one-time two-week grace period through August 10, 2026 for this first challenge, since the process is still being organized. The tapeout date itself is fixed, so late proposals simply mean less design time.

Challenge #2 detailed milestones: IHP SG13CMOS5L

DateMilestone
Jul 13, 2026Challenge launches
Jul 13–27, 2026Write proposals
Jul 27, 2026Proposals due (grace period through Aug 10, 2026)
Jul 27–Aug 31, 2026Schematic design & pre-layout verification
Week of Aug 31, 2026Schematic design review
Aug 31–Sep 28, 2026Layout & post-layout verification
Week of Sep 28, 2026Layout design review
Sep 28–Oct 19, 2026Chip top-level integration
Week of Oct 19, 2026Final design review
Nov 9, 2026IHP tapeout
Nov 16, 2026Test prep work begins
May 10, 2027Return from manufacture; packaging & assembly
Jun 28, 2027Parts shipped to designers; testing & characterization begins
Aug 30, 2027Test results due back

All five challenges at a glance

Challenge #1 was the original Efabless-run Sky130 challenge in 2024, already completed; dozens of analog circuits taped out across two test chips. Challenges #2–#6 below are the new Open Circuit Design-run series, restoring one challenge for each PDK and adding a second round for each.

ChallengePDKPlatformLaunchProposals DueStatus
#2IHP SG13CMOS5LIHPJul 13, 2026Jul 27, 2026In progress
#3GF180MCUWafer.SpaceAug 17, 2026Aug 31, 2026Upcoming
#4Sky130Chip FoundryNov 9, 2027Nov 23, 2027Upcoming
#5GF180MCUWafer.SpaceJan 4, 2027Jan 18, 2027Upcoming
#6IHP SG13CMOS5LIHPJun 21, 2027Jul 5, 2027Upcoming

Detailed milestone schedules for Challenges #3–#6 will be published closer to each launch date, following roughly the same 17–18 week pattern shown above for Challenge #2. Any changes to dates will be published here and announced on fossi-chat.org/#chipalooza.


Note that IHP tapeouts are scheduled several years in advance. The schedules for Wafer.Space and Chip Foundry are estimates based on past shuttle runs. Once information about tapeout schedules is available on the Wafer.Space or Chip Foundry websites, the schedules will be updated.