Challenge #2 (IHP SG13CMOS5L) is underway; the proposal field closed in August 2026 and schematic design is in progress, ahead of a November 9, 2026 tapeout. Challenge #3 (Wafer.Space GF180MCU) is currently accepting proposals, due August 31, 2026, ahead of a December 14, 2026 tapeout.
Challenge #2 detailed milestones: IHP SG13CMOS5L
| Date | Milestone |
|---|---|
| Jul 13, 2026 | Challenge launches |
| Jul 13–27, 2026 | Write proposals |
| Jul 27, 2026 | Proposals due (grace period through Aug 10, 2026) |
| Jul 27–Aug 31, 2026 | Schematic design & pre-layout verification |
| Week of Aug 31, 2026 | Schematic design review |
| Aug 31–Sep 28, 2026 | Layout & post-layout verification |
| Week of Sep 28, 2026 | Layout design review |
| Sep 28–Oct 19, 2026 | Chip top-level integration |
| Week of Oct 19, 2026 | Final design review |
| Nov 9, 2026 | IHP tapeout |
| Nov 16, 2026 | Test prep work begins |
| May 10, 2027 | Return from manufacture; packaging & assembly |
| Jun 28, 2027 | Parts shipped to designers; testing & characterization begins |
| Aug 30, 2027 | Test results due back |
Post-tapeout milestones (packaging, shipping, and testing dates) will be added once set.