Array Architecture

In an attempt to answer questions about the viability of an FPAA using antifuse technology in a digital process, we have designed a test structure to be fabricated on the Actel RT-SX process, incorporating twelve analog modules in a 3 x 4 array, which will allow us to test both continuous-time and switched-capacitor designs of numerous standard spaceflight applications, including pulse shaping, analog-to-digital and digital-to-analog conversion, modulators, oscillators, and filters.

The design of a single block incorporates circuit components as resources which can be connected into the circuit individually using antifuses. When unprogrammed, the resources are decoupled from the circuit except through the small antifuse capacitance. Our FPAA analog module design contains the following resources:

1

operational amplifier

4

programmable resistors

8

progammable capacitor arrays (6-bit resolution)

32

complementary MOS switches

The operational amplifier is a two-stage differential design for a digital process published in Yoshizawa, et al. [3], modified as necessary to meet design rules and maintain stability over the range of output loading capacitances possible with programming of the PCA. A continuous-time, rather than switched-capacitor, circuit performs common-mode feedback (CMFB); it consumes more power but allows the amplifier to be used in continuous-time as well as switched-capacitor circuit configurations. In a production version it would be desirable to reprogram the amplifier circuit for optimum performance under varying conditions, such as speed for use as a comparator.

Figure 1 shows the programmable capacitor array schematic used. Figure 5 shows the remainder of the resources,

  

Figure 5: Programmable resistor and switch resources.

while Figure 6 shows one side of the differential analog block

  

Figure 6: Configurable Analog Block (CAB) (only one side of differential architecture shown).

architecture (apart from the amplifier, one side is a mirror image of the other). Antifuse connections are not shown in the figure. Note that the row of switch resources acts as a barrier between the analog signal routing network and the digital signal routing network, helping to reduce digital noise coupling to the analog portion of the FPAA. Figure 7 shows two complete CABs as connected in one column of the test chip, including the vertical routing network and the antifuse connections.

  

Figure 7: Architecture of the FPAA test chip, showing one column containing two CABs, with routing network and antifuses.

Last updated: October 13, 1999 at 3:06pm